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git01.mediatek.com / filogic / uboot / 514628ce926c329c2e5736b7ed0ae590e1614da1 / . / arch / arm / dts / am4372-u-boot.dtsi
blob: 0c498bcf085cbe3a8c47295ba23e7a2792262e63 [file] [log] [blame]
Jean-Jacques Hiblot00c7a962018-12-04 11:30:52 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame]3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
Jean-Jacques Hiblot00c7a962018-12-04 11:30:52 +0100[diff] [blame]4 */
5
Jean-Jacques Hiblot5f717df2019-01-24 15:42:51 +0100[diff] [blame]6/{
7 aliases {
8 usb0 = &usb1;
9 usb1 = &usb2;
10 };
11};
12
Jean-Jacques Hiblot00c7a962018-12-04 11:30:52 +0100[diff] [blame]13&am43xx_control_usb2phy1 {
14 compatible = "ti,control-phy-usb2-am437", "syscon";
15};
16
17&am43xx_control_usb2phy2 {
18 compatible = "ti,control-phy-usb2-am437", "syscon";
19};
20
21&ocp2scp0 {
22 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp", "simple-bus";
23};
24
25&ocp2scp1 {
26 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp", "simple-bus";
27};
Jean-Jacques Hiblot2943afa2018-12-04 11:30:53 +0100[diff] [blame]28
29&dwc3_1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Jean-Jacques Hiblot2943afa2018-12-04 11:30:53 +0100[diff] [blame]31};
32
33&usb1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Jean-Jacques Hiblot2943afa2018-12-04 11:30:53 +0100[diff] [blame]35};
36
37&usb2_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Jean-Jacques Hiblot2943afa2018-12-04 11:30:53 +0100[diff] [blame]39};
40
41&am43xx_control_usb2phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Jean-Jacques Hiblot2943afa2018-12-04 11:30:53 +0100[diff] [blame]43};
44
45&ocp2scp0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Jean-Jacques Hiblot2943afa2018-12-04 11:30:53 +0100[diff] [blame]47};
Jean-Jacques Hiblot351164d2019-01-24 15:42:52 +0100[diff] [blame]48
49&dwc3_2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Jean-Jacques Hiblot351164d2019-01-24 15:42:52 +0100[diff] [blame]51};
52
53&usb2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Jean-Jacques Hiblot351164d2019-01-24 15:42:52 +0100[diff] [blame]55};
56
57&usb2_phy2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Jean-Jacques Hiblot351164d2019-01-24 15:42:52 +0100[diff] [blame]59};
60
61&am43xx_control_usb2phy2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Jean-Jacques Hiblot351164d2019-01-24 15:42:52 +0100[diff] [blame]63};
64
65&ocp2scp1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Jean-Jacques Hiblot351164d2019-01-24 15:42:52 +0100[diff] [blame]67};