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Pali Rohár4669df32021-12-21 12:20:18 +01001// SPDX-License-Identifier: GPL-2.0+
Marek Behún1c657bc2024-04-04 09:50:58 +02002/*
3 * Copyright (C) 2021 Pali Rohár <pali@kernel.org>
4 * Copyright (C) 2024 Marek Behún <kabel@kernel.org>
5 */
Pali Rohár4669df32021-12-21 12:20:18 +01006
7#include <common.h>
8#include <dm.h>
Marek Behún1c657bc2024-04-04 09:50:58 +02009#include <dm/lists.h>
10#include <regmap.h>
Pali Rohár4669df32021-12-21 12:20:18 +010011#include <reset-uclass.h>
Marek Behún1c657bc2024-04-04 09:50:58 +020012#include <syscon.h>
Pali Rohár4669df32021-12-21 12:20:18 +010013#include <asm/io.h>
14
15#define MVEBU_SOC_CONTROL_1_REG 0x4
16
17#define MVEBU_PCIE_ID 0
18
Pali Rohár4669df32021-12-21 12:20:18 +010019static int mvebu_reset_of_xlate(struct reset_ctl *rst,
20 struct ofnode_phandle_args *args)
21{
22 if (args->args_count < 2)
23 return -EINVAL;
24
25 rst->id = args->args[0];
26 rst->data = args->args[1];
27
28 /* Currently only PCIe is implemented */
29 if (rst->id != MVEBU_PCIE_ID)
30 return -EINVAL;
31
32 /* Four PCIe enable bits are shared across more PCIe links */
33 if (!(rst->data >= 0 && rst->data <= 3))
34 return -EINVAL;
35
36 return 0;
37}
38
39static int mvebu_reset_request(struct reset_ctl *rst)
40{
41 return 0;
42}
43
44static int mvebu_reset_free(struct reset_ctl *rst)
45{
46 return 0;
47}
48
49static int mvebu_reset_assert(struct reset_ctl *rst)
50{
Marek Behún1c657bc2024-04-04 09:50:58 +020051 struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
Pali Rohár4669df32021-12-21 12:20:18 +010052
Marek Behún1c657bc2024-04-04 09:50:58 +020053 return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG,
54 BIT(rst->data), 0);
Pali Rohár4669df32021-12-21 12:20:18 +010055}
56
57static int mvebu_reset_deassert(struct reset_ctl *rst)
58{
Marek Behún1c657bc2024-04-04 09:50:58 +020059 struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
Pali Rohár4669df32021-12-21 12:20:18 +010060
Marek Behún1c657bc2024-04-04 09:50:58 +020061 return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG,
62 BIT(rst->data), BIT(rst->data));
Pali Rohár4669df32021-12-21 12:20:18 +010063}
64
65static int mvebu_reset_status(struct reset_ctl *rst)
66{
Marek Behún1c657bc2024-04-04 09:50:58 +020067 struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
68 uint val;
69 int ret;
Pali Rohár4669df32021-12-21 12:20:18 +010070
Marek Behún1c657bc2024-04-04 09:50:58 +020071 ret = regmap_read(regmap, MVEBU_SOC_CONTROL_1_REG, &val);
72 if (ret < 0)
73 return ret;
Pali Rohár4669df32021-12-21 12:20:18 +010074
Marek Behún1c657bc2024-04-04 09:50:58 +020075 return !(val & BIT(rst->data));
Pali Rohár4669df32021-12-21 12:20:18 +010076}
77
Pali Rohár32301ee2022-09-09 14:41:28 +020078static const struct reset_ops mvebu_reset_ops = {
Pali Rohár4669df32021-12-21 12:20:18 +010079 .of_xlate = mvebu_reset_of_xlate,
80 .request = mvebu_reset_request,
81 .rfree = mvebu_reset_free,
82 .rst_assert = mvebu_reset_assert,
83 .rst_deassert = mvebu_reset_deassert,
84 .rst_status = mvebu_reset_status,
85};
86
87U_BOOT_DRIVER(mvebu_reset) = {
88 .name = "mvebu-reset",
89 .id = UCLASS_RESET,
Pali Rohár4669df32021-12-21 12:20:18 +010090 .ops = &mvebu_reset_ops,
91};
Marek Behún1c657bc2024-04-04 09:50:58 +020092
93static int mvebu_syscon_bind(struct udevice *dev)
94{
95 /* bind also mvebu-reset, with the same ofnode */
96 return device_bind_driver_to_node(dev, "mvebu-reset", "mvebu-reset",
97 dev_ofnode(dev), NULL);
98}
99
100static const struct udevice_id mvebu_syscon_of_match[] = {
101 { .compatible = "marvell,armada-370-xp-system-controller" },
102 { .compatible = "marvell,armada-375-system-controller" },
103 { .compatible = "marvell,armada-380-system-controller" },
104 { .compatible = "marvell,armada-390-system-controller" },
105 { },
106};
107
108U_BOOT_DRIVER(mvebu_syscon) = {
109 .name = "mvebu-system-controller",
110 .id = UCLASS_SYSCON,
111 .of_match = mvebu_syscon_of_match,
112 .bind = mvebu_syscon_bind,
113};