Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2016 Google, Inc |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <clk-uclass.h> |
| 8 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 9 | #include <log.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 10 | #include <asm/global_data.h> |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 11 | #include <asm/io.h> |
| 12 | #include <asm/arch/scu_ast2500.h> |
| 13 | #include <dm/lists.h> |
Ryan Chen | 5e6c9f0 | 2020-08-31 14:03:03 +0800 | [diff] [blame] | 14 | #include <dt-bindings/clock/aspeed-clock.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 15 | #include <linux/delay.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 16 | #include <linux/err.h> |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 17 | |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 18 | /* |
| 19 | * MAC Clock Delay settings, taken from Aspeed SDK |
| 20 | */ |
| 21 | #define RGMII_TXCLK_ODLY 8 |
| 22 | #define RMII_RXCLK_IDLY 2 |
| 23 | |
| 24 | /* |
| 25 | * TGMII Clock Duty constants, taken from Aspeed SDK |
| 26 | */ |
| 27 | #define RGMII2_TXCK_DUTY 0x66 |
| 28 | #define RGMII1_TXCK_DUTY 0x64 |
| 29 | |
| 30 | #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) |
| 31 | |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 32 | DECLARE_GLOBAL_DATA_PTR; |
| 33 | |
| 34 | /* |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 35 | * Clock divider/multiplier configuration struct. |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 36 | * For H-PLL and M-PLL the formula is |
| 37 | * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) |
| 38 | * M - Numerator |
| 39 | * N - Denumerator |
| 40 | * P - Post Divider |
| 41 | * They have the same layout in their control register. |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 42 | * |
| 43 | * D-PLL and D2-PLL have extra divider (OD + 1), which is not |
| 44 | * yet needed and ignored by clock configurations. |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 45 | */ |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 46 | struct ast2500_div_config { |
| 47 | unsigned int num; |
| 48 | unsigned int denum; |
| 49 | unsigned int post_div; |
| 50 | }; |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 51 | |
| 52 | /* |
| 53 | * Get the rate of the M-PLL clock from input clock frequency and |
| 54 | * the value of the M-PLL Parameter Register. |
| 55 | */ |
| 56 | static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg) |
| 57 | { |
maxims@google.com | a91f1d2 | 2017-04-17 12:00:33 -0700 | [diff] [blame] | 58 | const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT; |
| 59 | const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK) |
| 60 | >> SCU_MPLL_DENUM_SHIFT; |
| 61 | const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) |
| 62 | >> SCU_MPLL_POST_SHIFT; |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 63 | |
maxims@google.com | d067217 | 2017-01-30 11:35:04 -0800 | [diff] [blame] | 64 | return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | /* |
| 68 | * Get the rate of the H-PLL clock from input clock frequency and |
| 69 | * the value of the H-PLL Parameter Register. |
| 70 | */ |
| 71 | static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg) |
| 72 | { |
maxims@google.com | a91f1d2 | 2017-04-17 12:00:33 -0700 | [diff] [blame] | 73 | const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT; |
| 74 | const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK) |
| 75 | >> SCU_HPLL_DENUM_SHIFT; |
| 76 | const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK) |
| 77 | >> SCU_HPLL_POST_SHIFT; |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 78 | |
maxims@google.com | d067217 | 2017-01-30 11:35:04 -0800 | [diff] [blame] | 79 | return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 80 | } |
| 81 | |
| 82 | static ulong ast2500_get_clkin(struct ast2500_scu *scu) |
| 83 | { |
| 84 | return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ |
| 85 | ? 25 * 1000 * 1000 : 24 * 1000 * 1000; |
| 86 | } |
| 87 | |
| 88 | /** |
| 89 | * Get current rate or uart clock |
| 90 | * |
| 91 | * @scu SCU registers |
| 92 | * @uart_index UART index, 1-5 |
| 93 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 94 | * Return: current setting for uart clock rate |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 95 | */ |
| 96 | static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index) |
| 97 | { |
| 98 | /* |
| 99 | * ast2500 datasheet is very confusing when it comes to UART clocks, |
| 100 | * especially when CLKIN = 25 MHz. The settings are in |
| 101 | * different registers and it is unclear how they interact. |
| 102 | * |
| 103 | * This has only been tested with default settings and CLKIN = 24 MHz. |
| 104 | */ |
| 105 | ulong uart_clkin; |
| 106 | |
| 107 | if (readl(&scu->misc_ctrl2) & |
| 108 | (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT))) |
| 109 | uart_clkin = 192 * 1000 * 1000; |
| 110 | else |
| 111 | uart_clkin = 24 * 1000 * 1000; |
| 112 | |
| 113 | if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13) |
| 114 | uart_clkin /= 13; |
| 115 | |
| 116 | return uart_clkin; |
| 117 | } |
| 118 | |
| 119 | static ulong ast2500_clk_get_rate(struct clk *clk) |
| 120 | { |
| 121 | struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); |
| 122 | ulong clkin = ast2500_get_clkin(priv->scu); |
| 123 | ulong rate; |
| 124 | |
| 125 | switch (clk->id) { |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 126 | case ASPEED_CLK_HPLL: |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 127 | /* |
| 128 | * This ignores dynamic/static slowdown of ARMCLK and may |
| 129 | * be inaccurate. |
| 130 | */ |
| 131 | rate = ast2500_get_hpll_rate(clkin, |
| 132 | readl(&priv->scu->h_pll_param)); |
| 133 | break; |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 134 | case ASPEED_CLK_MPLL: |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 135 | rate = ast2500_get_mpll_rate(clkin, |
| 136 | readl(&priv->scu->m_pll_param)); |
| 137 | break; |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 138 | case ASPEED_CLK_APB: |
maxims@google.com | 995167b | 2017-04-17 12:00:29 -0700 | [diff] [blame] | 139 | { |
| 140 | ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) |
maxims@google.com | a91f1d2 | 2017-04-17 12:00:33 -0700 | [diff] [blame] | 141 | & SCU_PCLK_DIV_MASK) |
| 142 | >> SCU_PCLK_DIV_SHIFT); |
maxims@google.com | 995167b | 2017-04-17 12:00:29 -0700 | [diff] [blame] | 143 | rate = ast2500_get_hpll_rate(clkin, |
maxims@google.com | a91f1d2 | 2017-04-17 12:00:33 -0700 | [diff] [blame] | 144 | readl(&priv-> |
| 145 | scu->h_pll_param)); |
maxims@google.com | 995167b | 2017-04-17 12:00:29 -0700 | [diff] [blame] | 146 | rate = rate / apb_div; |
| 147 | } |
| 148 | break; |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 149 | case ASPEED_CLK_SDIO: |
Eddie James | b7d76ac | 2019-08-15 14:29:37 -0500 | [diff] [blame] | 150 | { |
| 151 | ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) |
| 152 | & SCU_SDCLK_DIV_MASK) |
| 153 | >> SCU_SDCLK_DIV_SHIFT); |
| 154 | rate = ast2500_get_hpll_rate(clkin, |
| 155 | readl(&priv-> |
| 156 | scu->h_pll_param)); |
| 157 | rate = rate / apb_div; |
| 158 | } |
| 159 | break; |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 160 | case ASPEED_CLK_GATE_UART1CLK: |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 161 | rate = ast2500_get_uart_clk_rate(priv->scu, 1); |
| 162 | break; |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 163 | case ASPEED_CLK_GATE_UART2CLK: |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 164 | rate = ast2500_get_uart_clk_rate(priv->scu, 2); |
| 165 | break; |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 166 | case ASPEED_CLK_GATE_UART3CLK: |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 167 | rate = ast2500_get_uart_clk_rate(priv->scu, 3); |
| 168 | break; |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 169 | case ASPEED_CLK_GATE_UART4CLK: |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 170 | rate = ast2500_get_uart_clk_rate(priv->scu, 4); |
| 171 | break; |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 172 | case ASPEED_CLK_GATE_UART5CLK: |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 173 | rate = ast2500_get_uart_clk_rate(priv->scu, 5); |
| 174 | break; |
| 175 | default: |
| 176 | return -ENOENT; |
| 177 | } |
| 178 | |
| 179 | return rate; |
| 180 | } |
| 181 | |
Cédric Le Goater | d7f3789 | 2018-10-29 07:06:41 +0100 | [diff] [blame] | 182 | struct ast2500_clock_config { |
| 183 | ulong input_rate; |
| 184 | ulong rate; |
| 185 | struct ast2500_div_config cfg; |
| 186 | }; |
| 187 | |
| 188 | static const struct ast2500_clock_config ast2500_clock_config_defaults[] = { |
| 189 | { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } }, |
| 190 | }; |
| 191 | |
| 192 | static bool ast2500_get_clock_config_default(ulong input_rate, |
| 193 | ulong requested_rate, |
| 194 | struct ast2500_div_config *cfg) |
| 195 | { |
| 196 | int i; |
| 197 | |
| 198 | for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) { |
| 199 | const struct ast2500_clock_config *default_cfg = |
| 200 | &ast2500_clock_config_defaults[i]; |
| 201 | if (default_cfg->input_rate == input_rate && |
| 202 | default_cfg->rate == requested_rate) { |
| 203 | *cfg = default_cfg->cfg; |
| 204 | return true; |
| 205 | } |
| 206 | } |
| 207 | |
| 208 | return false; |
| 209 | } |
| 210 | |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 211 | /* |
| 212 | * @input_rate - the rate of input clock in Hz |
| 213 | * @requested_rate - desired output rate in Hz |
| 214 | * @div - this is an IN/OUT parameter, at input all fields of the config |
| 215 | * need to be set to their maximum allowed values. |
| 216 | * The result (the best config we could find), would also be returned |
| 217 | * in this structure. |
| 218 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 219 | * Return: The clock rate, when the resulting div_config is used. |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 220 | */ |
| 221 | static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, |
| 222 | struct ast2500_div_config *cfg) |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 223 | { |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 224 | /* |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 225 | * The assumption is that kHz precision is good enough and |
| 226 | * also enough to avoid overflow when multiplying. |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 227 | */ |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 228 | const ulong input_rate_khz = input_rate / 1000; |
| 229 | const ulong rate_khz = requested_rate / 1000; |
| 230 | const struct ast2500_div_config max_vals = *cfg; |
| 231 | struct ast2500_div_config it = { 0, 0, 0 }; |
| 232 | ulong delta = rate_khz; |
| 233 | ulong new_rate_khz = 0; |
| 234 | |
Cédric Le Goater | d7f3789 | 2018-10-29 07:06:41 +0100 | [diff] [blame] | 235 | /* |
| 236 | * Look for a well known frequency first. |
| 237 | */ |
| 238 | if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg)) |
| 239 | return requested_rate; |
| 240 | |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 241 | for (; it.denum <= max_vals.denum; ++it.denum) { |
| 242 | for (it.post_div = 0; it.post_div <= max_vals.post_div; |
| 243 | ++it.post_div) { |
| 244 | it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) |
| 245 | * (it.denum + 1); |
| 246 | if (it.num > max_vals.num) |
| 247 | continue; |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 248 | |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 249 | new_rate_khz = (input_rate_khz |
| 250 | * ((it.num + 1) / (it.denum + 1))) |
| 251 | / (it.post_div + 1); |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 252 | |
| 253 | /* Keep the rate below requested one. */ |
| 254 | if (new_rate_khz > rate_khz) |
| 255 | continue; |
| 256 | |
| 257 | if (new_rate_khz - rate_khz < delta) { |
| 258 | delta = new_rate_khz - rate_khz; |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 259 | *cfg = it; |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 260 | if (delta == 0) |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 261 | return new_rate_khz * 1000; |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 262 | } |
| 263 | } |
| 264 | } |
| 265 | |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 266 | return new_rate_khz * 1000; |
| 267 | } |
| 268 | |
| 269 | static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate) |
| 270 | { |
| 271 | ulong clkin = ast2500_get_clkin(scu); |
| 272 | u32 mpll_reg; |
| 273 | struct ast2500_div_config div_cfg = { |
maxims@google.com | a91f1d2 | 2017-04-17 12:00:33 -0700 | [diff] [blame] | 274 | .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT), |
| 275 | .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT), |
| 276 | .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 277 | }; |
| 278 | |
| 279 | ast2500_calc_clock_config(clkin, rate, &div_cfg); |
| 280 | |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 281 | mpll_reg = readl(&scu->m_pll_param); |
maxims@google.com | a91f1d2 | 2017-04-17 12:00:33 -0700 | [diff] [blame] | 282 | mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK |
| 283 | | SCU_MPLL_DENUM_MASK); |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 284 | mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) |
| 285 | | (div_cfg.num << SCU_MPLL_NUM_SHIFT) |
| 286 | | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT); |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 287 | |
maxims@google.com | adea66c | 2017-04-17 12:00:23 -0700 | [diff] [blame] | 288 | ast_scu_unlock(scu); |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 289 | writel(mpll_reg, &scu->m_pll_param); |
maxims@google.com | adea66c | 2017-04-17 12:00:23 -0700 | [diff] [blame] | 290 | ast_scu_lock(scu); |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 291 | |
| 292 | return ast2500_get_mpll_rate(clkin, mpll_reg); |
| 293 | } |
| 294 | |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 295 | static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index) |
| 296 | { |
| 297 | ulong clkin = ast2500_get_clkin(scu); |
| 298 | ulong hpll_rate = ast2500_get_hpll_rate(clkin, |
| 299 | readl(&scu->h_pll_param)); |
| 300 | ulong required_rate; |
| 301 | u32 hwstrap; |
| 302 | u32 divisor; |
| 303 | u32 reset_bit; |
| 304 | u32 clkstop_bit; |
| 305 | |
| 306 | /* |
| 307 | * According to data sheet, for 10/100 mode the MAC clock frequency |
| 308 | * should be at least 25MHz and for 1000 mode at least 100MHz |
| 309 | */ |
| 310 | hwstrap = readl(&scu->hwstrap); |
| 311 | if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII)) |
| 312 | required_rate = 100 * 1000 * 1000; |
| 313 | else |
| 314 | required_rate = 25 * 1000 * 1000; |
| 315 | |
| 316 | divisor = hpll_rate / required_rate; |
| 317 | |
| 318 | if (divisor < 4) { |
| 319 | /* Clock can't run fast enough, but let's try anyway */ |
| 320 | debug("MAC clock too slow\n"); |
| 321 | divisor = 4; |
| 322 | } else if (divisor > 16) { |
| 323 | /* Can't slow down the clock enough, but let's try anyway */ |
| 324 | debug("MAC clock too fast\n"); |
| 325 | divisor = 16; |
| 326 | } |
| 327 | |
| 328 | switch (index) { |
| 329 | case 1: |
| 330 | reset_bit = SCU_SYSRESET_MAC1; |
| 331 | clkstop_bit = SCU_CLKSTOP_MAC1; |
| 332 | break; |
| 333 | case 2: |
| 334 | reset_bit = SCU_SYSRESET_MAC2; |
| 335 | clkstop_bit = SCU_CLKSTOP_MAC2; |
| 336 | break; |
| 337 | default: |
| 338 | return -EINVAL; |
| 339 | } |
| 340 | |
| 341 | ast_scu_unlock(scu); |
| 342 | clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK, |
| 343 | ((divisor - 2) / 2) << SCU_MACCLK_SHIFT); |
| 344 | |
| 345 | /* |
| 346 | * Disable MAC, start its clock and re-enable it. |
| 347 | * The procedure and the delays (100us & 10ms) are |
| 348 | * specified in the datasheet. |
| 349 | */ |
| 350 | setbits_le32(&scu->sysreset_ctrl1, reset_bit); |
| 351 | udelay(100); |
| 352 | clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); |
| 353 | mdelay(10); |
| 354 | clrbits_le32(&scu->sysreset_ctrl1, reset_bit); |
| 355 | |
| 356 | writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT) |
| 357 | | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT), |
| 358 | &scu->clk_duty_sel); |
| 359 | |
| 360 | ast_scu_lock(scu); |
| 361 | |
| 362 | return required_rate; |
| 363 | } |
| 364 | |
| 365 | static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate) |
| 366 | { |
| 367 | /* |
| 368 | * The values and the meaning of the next three |
| 369 | * parameters are undocumented. Taken from Aspeed SDK. |
Cédric Le Goater | d7f3789 | 2018-10-29 07:06:41 +0100 | [diff] [blame] | 370 | * |
| 371 | * TODO(clg@kaod.org): the SIP and SIC values depend on the |
| 372 | * Numerator value |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 373 | */ |
| 374 | const u32 d2_pll_ext_param = 0x2c; |
| 375 | const u32 d2_pll_sip = 0x11; |
| 376 | const u32 d2_pll_sic = 0x18; |
| 377 | u32 clk_delay_settings = |
| 378 | (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT) |
| 379 | | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT) |
| 380 | | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) |
| 381 | | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT); |
| 382 | struct ast2500_div_config div_cfg = { |
| 383 | .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT, |
| 384 | .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT, |
| 385 | .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT, |
| 386 | }; |
| 387 | ulong clkin = ast2500_get_clkin(scu); |
| 388 | ulong new_rate; |
| 389 | |
| 390 | ast_scu_unlock(scu); |
| 391 | writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT) |
| 392 | | SCU_D2PLL_EXT1_OFF |
| 393 | | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]); |
| 394 | |
| 395 | /* |
| 396 | * Select USB2.0 port1 PHY clock as a clock source for GCRT. |
| 397 | * This would disconnect it from D2-PLL. |
| 398 | */ |
| 399 | clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF, |
| 400 | SCU_MISC_GCRT_USB20CLK); |
| 401 | |
| 402 | new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg); |
| 403 | writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT) |
| 404 | | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT) |
| 405 | | (div_cfg.num << SCU_D2PLL_NUM_SHIFT) |
| 406 | | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT) |
| 407 | | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT), |
| 408 | &scu->d2_pll_param); |
| 409 | |
| 410 | clrbits_le32(&scu->d2_pll_ext_param[0], |
| 411 | SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET); |
| 412 | |
| 413 | clrsetbits_le32(&scu->misc_ctrl2, |
| 414 | SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL |
| 415 | | SCU_MISC2_RGMII_CLKDIV_MASK | |
| 416 | SCU_MISC2_RMII_CLKDIV_MASK, |
| 417 | (4 << SCU_MISC2_RMII_CLKDIV_SHIFT)); |
| 418 | |
| 419 | writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay); |
| 420 | writel(clk_delay_settings, &scu->mac_clk_delay_100M); |
| 421 | writel(clk_delay_settings, &scu->mac_clk_delay_10M); |
| 422 | |
| 423 | ast_scu_lock(scu); |
| 424 | |
| 425 | return new_rate; |
| 426 | } |
| 427 | |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 428 | static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) |
| 429 | { |
| 430 | struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); |
| 431 | |
| 432 | ulong new_rate; |
| 433 | switch (clk->id) { |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 434 | case ASPEED_CLK_MPLL: |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 435 | new_rate = ast2500_configure_ddr(priv->scu, rate); |
| 436 | break; |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 437 | case ASPEED_CLK_D2PLL: |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 438 | new_rate = ast2500_configure_d2pll(priv->scu, rate); |
| 439 | break; |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 440 | default: |
| 441 | return -ENOENT; |
| 442 | } |
| 443 | |
| 444 | return new_rate; |
| 445 | } |
| 446 | |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 447 | static int ast2500_clk_enable(struct clk *clk) |
| 448 | { |
| 449 | struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); |
| 450 | |
| 451 | switch (clk->id) { |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 452 | case ASPEED_CLK_SDIO: |
Eddie James | b7d76ac | 2019-08-15 14:29:37 -0500 | [diff] [blame] | 453 | if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) { |
| 454 | ast_scu_unlock(priv->scu); |
| 455 | |
| 456 | setbits_le32(&priv->scu->sysreset_ctrl1, |
| 457 | SCU_SYSRESET_SDIO); |
| 458 | udelay(100); |
| 459 | clrbits_le32(&priv->scu->clk_stop_ctrl1, |
| 460 | SCU_CLKSTOP_SDCLK); |
| 461 | mdelay(10); |
| 462 | clrbits_le32(&priv->scu->sysreset_ctrl1, |
| 463 | SCU_SYSRESET_SDIO); |
| 464 | |
| 465 | ast_scu_lock(priv->scu); |
| 466 | } |
| 467 | break; |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 468 | /* |
| 469 | * For MAC clocks the clock rate is |
| 470 | * configured based on whether RGMII or RMII mode has been selected |
| 471 | * through hardware strapping. |
| 472 | */ |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 473 | case ASPEED_CLK_GATE_MAC1CLK: |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 474 | ast2500_configure_mac(priv->scu, 1); |
| 475 | break; |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 476 | case ASPEED_CLK_GATE_MAC2CLK: |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 477 | ast2500_configure_mac(priv->scu, 2); |
| 478 | break; |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 479 | case ASPEED_CLK_D2PLL: |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 480 | ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); |
Cédric Le Goater | 62b4bfd | 2018-10-29 07:06:37 +0100 | [diff] [blame] | 481 | break; |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 482 | default: |
| 483 | return -ENOENT; |
| 484 | } |
| 485 | |
| 486 | return 0; |
| 487 | } |
| 488 | |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 489 | struct clk_ops ast2500_clk_ops = { |
| 490 | .get_rate = ast2500_clk_get_rate, |
| 491 | .set_rate = ast2500_clk_set_rate, |
maxims@google.com | 15016af | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 492 | .enable = ast2500_clk_enable, |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 493 | }; |
| 494 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 495 | static int ast2500_clk_of_to_plat(struct udevice *dev) |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 496 | { |
| 497 | struct ast2500_clk_priv *priv = dev_get_priv(dev); |
| 498 | |
Ryan Chen | 1e4a5c1 | 2020-08-31 14:03:04 +0800 | [diff] [blame] | 499 | priv->scu = devfdt_get_addr_ptr(dev); |
| 500 | if (IS_ERR(priv->scu)) |
| 501 | return PTR_ERR(priv->scu); |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 502 | |
| 503 | return 0; |
| 504 | } |
| 505 | |
| 506 | static int ast2500_clk_bind(struct udevice *dev) |
| 507 | { |
| 508 | int ret; |
| 509 | |
| 510 | /* The reset driver does not have a device node, so bind it here */ |
| 511 | ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); |
| 512 | if (ret) |
| 513 | debug("Warning: No reset driver: ret=%d\n", ret); |
| 514 | |
| 515 | return 0; |
| 516 | } |
| 517 | |
| 518 | static const struct udevice_id ast2500_clk_ids[] = { |
| 519 | { .compatible = "aspeed,ast2500-scu" }, |
| 520 | { } |
| 521 | }; |
| 522 | |
| 523 | U_BOOT_DRIVER(aspeed_ast2500_scu) = { |
| 524 | .name = "aspeed_ast2500_scu", |
| 525 | .id = UCLASS_CLK, |
| 526 | .of_match = ast2500_clk_ids, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 527 | .priv_auto = sizeof(struct ast2500_clk_priv), |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 528 | .ops = &ast2500_clk_ops, |
| 529 | .bind = ast2500_clk_bind, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 530 | .of_to_plat = ast2500_clk_of_to_plat, |
maxims@google.com | 2d5a2ad | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 531 | }; |