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wdenkd9fd6ff2002-10-11 08:43:32 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <asm/arch/pxa-regs.h>
29#include <common.h>
30
Wolfgang Denk6405a152006-03-31 18:32:53 +020031DECLARE_GLOBAL_DATA_PTR;
32
wdenkd9fd6ff2002-10-11 08:43:32 +000033/* ------------------------------------------------------------------------- */
34
35
36/* local prototypes */
37void set_led (int led, int color);
38void error_code_halt (int code);
39int init_sio (int led, unsigned long base);
40inline void cradle_outb (unsigned short val, unsigned long base,
41 unsigned long reg);
42inline unsigned char cradle_inb (unsigned long base, unsigned long reg);
43inline void sleep (int i);
44
45inline void
46/**********************************************************/
47sleep (int i)
48/**********************************************************/
49{
50 while (i--) {
51 udelay (1000000);
52 }
53}
54
55void
56/**********************************************************/
57error_code_halt (int code)
58/**********************************************************/
59{
60 while (1) {
61 led_code (code, RED);
62 sleep (1);
63 led_code (0, OFF);
64 sleep (1);
65 }
66}
67
68void
69/**********************************************************/
70led_code (int code, int color)
71/**********************************************************/
72{
73 int i;
74
75 code &= 0xf; /* only 4 leds */
76
77 for (i = 0; i < 4; i++) {
78 if (code & (1 << i)) {
79 set_led (i, color);
80 } else {
81 set_led (i, OFF);
82 }
83 }
84}
85
86void
87/**********************************************************/
88set_led (int led, int color)
89/**********************************************************/
90{
91 int shift = led * 2;
92 unsigned long mask = 0x3 << shift;
93
94 CRADLE_LED_CLR_REG = mask; /* clear bits */
95 CRADLE_LED_SET_REG = (color << shift); /* set bits */
96 udelay (5000);
97}
98
99inline void
100/**********************************************************/
101cradle_outb (unsigned short val, unsigned long base, unsigned long reg)
102/**********************************************************/
103{
104 *(volatile unsigned short *) (base + (reg * 2)) = val;
105}
106
107inline unsigned char
108/**********************************************************/
109cradle_inb (unsigned long base, unsigned long reg)
110/**********************************************************/
111{
112 unsigned short val;
113
114 val = *(volatile unsigned short *) (base + (reg * 2));
115 return (val & 0xff);
116}
117
118int
119/**********************************************************/
120init_sio (int led, unsigned long base)
121/**********************************************************/
122{
123 unsigned char val;
124
125 set_led (led, YELLOW);
126 val = cradle_inb (base, CRADLE_SIO_INDEX);
127 val = cradle_inb (base, CRADLE_SIO_INDEX);
128 if (val != 0) {
129 set_led (led, RED);
130 return -1;
131 }
132
133 /* map SCC2 to COM1 */
134 cradle_outb (0x01, base, CRADLE_SIO_INDEX);
135 cradle_outb (0x00, base, CRADLE_SIO_DATA);
136
137 /* enable SCC2 extended regs */
138 cradle_outb (0x40, base, CRADLE_SIO_INDEX);
139 cradle_outb (0xa0, base, CRADLE_SIO_DATA);
140
141 /* enable SCC2 clock multiplier */
142 cradle_outb (0x51, base, CRADLE_SIO_INDEX);
143 cradle_outb (0x04, base, CRADLE_SIO_DATA);
144
145 /* enable SCC2 */
146 cradle_outb (0x00, base, CRADLE_SIO_INDEX);
147 cradle_outb (0x04, base, CRADLE_SIO_DATA);
148
149 /* map SCC2 DMA to channel 0 */
150 cradle_outb (0x4f, base, CRADLE_SIO_INDEX);
151 cradle_outb (0x09, base, CRADLE_SIO_DATA);
152
153 /* read ID from SIO to check operation */
154 cradle_outb (0xe4, base, 0x3f8 + 0x3);
155 val = cradle_inb (base, 0x3f8 + 0x0);
156 if ((val & 0xf0) != 0x20) {
157 set_led (led, RED);
158 /* disable SCC2 */
159 cradle_outb (0, base, CRADLE_SIO_INDEX);
160 cradle_outb (0, base, CRADLE_SIO_DATA);
161 return -1;
162 }
163 /* set back to bank 0 */
164 cradle_outb (0, base, 0x3f8 + 0x3);
165 set_led (led, GREEN);
166 return 0;
167}
168
169/*
170 * Miscelaneous platform dependent initialisations
171 */
172
173int
174/**********************************************************/
wdenkda55c6e2004-01-20 23:12:12 +0000175board_late_init (void)
wdenkd9fd6ff2002-10-11 08:43:32 +0000176/**********************************************************/
177{
178 return (0);
179}
180
181int
182/**********************************************************/
183board_init (void)
184/**********************************************************/
185{
wdenkd9fd6ff2002-10-11 08:43:32 +0000186 led_code (0xf, YELLOW);
187
188 /* arch number of HHP Cradle */
wdenk767fbd42004-10-10 18:41:04 +0000189 gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE;
wdenkd9fd6ff2002-10-11 08:43:32 +0000190
191 /* adress of boot parameters */
192 gd->bd->bi_boot_params = 0xa0000100;
193
194 /* Init SIOs to enable SCC2 */
195 udelay (100000); /* delay makes it look neat */
196 init_sio (0, CRADLE_SIO1_PHYS);
197 udelay (100000);
198 init_sio (1, CRADLE_SIO2_PHYS);
199 udelay (100000);
200 init_sio (2, CRADLE_SIO3_PHYS);
201 udelay (100000);
202 set_led (3, GREEN);
203
204 return 1;
205}
206
207int
208/**********************************************************/
209dram_init (void)
210/**********************************************************/
211{
wdenkd9fd6ff2002-10-11 08:43:32 +0000212 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
213 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
214 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
215 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
216 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
217 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
218 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
219 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
220
221 return (PHYS_SDRAM_1_SIZE +
222 PHYS_SDRAM_2_SIZE +
223 PHYS_SDRAM_3_SIZE +
224 PHYS_SDRAM_4_SIZE );
225}