George McCollister | a4dd9bf | 2015-10-21 08:05:33 -0500 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
| 3 | /include/ "skeleton.dtsi" |
| 4 | /include/ "serial.dtsi" |
| 5 | /include/ "rtc.dtsi" |
Bin Meng | 38de020 | 2015-11-13 00:11:22 -0800 | [diff] [blame] | 6 | /include/ "tsc_timer.dtsi" |
George McCollister | a4dd9bf | 2015-10-21 08:05:33 -0500 | [diff] [blame] | 7 | |
| 8 | / { |
| 9 | model = "Advantech SOM-6896"; |
| 10 | compatible = "advantech,som-6896", "intel,broadwell"; |
| 11 | |
| 12 | aliases { |
Bin Meng | 4f8d4e9 | 2016-01-27 00:56:34 -0800 | [diff] [blame^] | 13 | spi0 = &spi; |
George McCollister | a4dd9bf | 2015-10-21 08:05:33 -0500 | [diff] [blame] | 14 | }; |
| 15 | |
| 16 | config { |
| 17 | silent_console = <0>; |
| 18 | }; |
| 19 | |
| 20 | chosen { |
| 21 | stdout-path = "/serial"; |
| 22 | }; |
| 23 | |
| 24 | pci { |
| 25 | compatible = "pci-x86"; |
| 26 | #address-cells = <3>; |
| 27 | #size-cells = <2>; |
| 28 | u-boot,dm-pre-reloc; |
| 29 | ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 |
| 30 | 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 |
| 31 | 0x01000000 0x0 0x2000 0x2000 0 0xe000>; |
George McCollister | a4dd9bf | 2015-10-21 08:05:33 -0500 | [diff] [blame] | 32 | |
Simon Glass | 3276163 | 2016-01-18 20:19:21 -0700 | [diff] [blame] | 33 | pch@1f,0 { |
| 34 | reg = <0x0000f800 0 0 0 0>; |
| 35 | compatible = "intel,pch9"; |
| 36 | |
Bin Meng | 4f8d4e9 | 2016-01-27 00:56:34 -0800 | [diff] [blame^] | 37 | spi: spi { |
Simon Glass | 3276163 | 2016-01-18 20:19:21 -0700 | [diff] [blame] | 38 | #address-cells = <1>; |
| 39 | #size-cells = <0>; |
| 40 | compatible = "intel,ich-spi"; |
| 41 | spi-flash@0 { |
| 42 | reg = <0>; |
| 43 | compatible = "winbond,w25q128", "spi-flash"; |
| 44 | memory-map = <0xff000000 0x01000000>; |
| 45 | }; |
| 46 | }; |
George McCollister | a4dd9bf | 2015-10-21 08:05:33 -0500 | [diff] [blame] | 47 | }; |
| 48 | }; |
Simon Glass | 3276163 | 2016-01-18 20:19:21 -0700 | [diff] [blame] | 49 | |
George McCollister | a4dd9bf | 2015-10-21 08:05:33 -0500 | [diff] [blame] | 50 | }; |