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git01.mediatek.com / filogic / uboot / 4f1ad22f48e083e08ec4b7b90a48195c014ca1e0 / . / drivers / pinctrl / rockchip / pinctrl_rk3368.c
blob: d299eb51e015e0c0fd1c35886e9248c581f3a363 [file] [log] [blame]
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]1/*
2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 * Author: Andy Yan <andy.yan@rock-chips.com>
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#include <common.h>
7#include <dm.h>
8#include <errno.h>
9#include <syscon.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/hardware.h>
13#include <asm/arch/grf_rk3368.h>
14#include <asm/arch/periph.h>
15#include <dm/pinctrl.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
Philipp Tomsich4f1ad222017-07-25 17:09:23 +0200[diff] [blame^]19/*GRF_GPIO0C_IOMUX*/
20enum {
21 GPIO0C7_SHIFT = 14,
22 GPIO0C7_MASK = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
23 GPIO0C7_GPIO = 0,
24 GPIO0C7_LCDC_D19 = (1 << GPIO0C7_SHIFT),
25 GPIO0C7_TRACE_D9 = (2 << GPIO0C7_SHIFT),
26 GPIO0C7_UART1_RTSN = (3 << GPIO0C7_SHIFT),
27
28 GPIO0C6_SHIFT = 12,
29 GPIO0C6_MASK = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
30 GPIO0C6_GPIO = 0,
31 GPIO0C6_LCDC_D18 = (1 << GPIO0C6_SHIFT),
32 GPIO0C6_TRACE_D8 = (2 << GPIO0C6_SHIFT),
33 GPIO0C6_UART1_CTSN = (3 << GPIO0C6_SHIFT),
34
35 GPIO0C5_SHIFT = 10,
36 GPIO0C5_MASK = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
37 GPIO0C5_GPIO = 0,
38 GPIO0C5_LCDC_D17 = (1 << GPIO0C5_SHIFT),
39 GPIO0C5_TRACE_D7 = (2 << GPIO0C5_SHIFT),
40 GPIO0C5_UART1_SOUT = (3 << GPIO0C5_SHIFT),
41
42 GPIO0C4_SHIFT = 8,
43 GPIO0C4_MASK = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
44 GPIO0C4_GPIO = 0,
45 GPIO0C4_LCDC_D16 = (1 << GPIO0C4_SHIFT),
46 GPIO0C4_TRACE_D6 = (2 << GPIO0C4_SHIFT),
47 GPIO0C4_UART1_SIN = (3 << GPIO0C4_SHIFT),
48
49 GPIO0C3_SHIFT = 6,
50 GPIO0C3_MASK = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
51 GPIO0C3_GPIO = 0,
52 GPIO0C3_LCDC_D15 = (1 << GPIO0C3_SHIFT),
53 GPIO0C3_TRACE_D5 = (2 << GPIO0C3_SHIFT),
54 GPIO0C3_MCU_JTAG_TDO = (3 << GPIO0C3_SHIFT),
55
56 GPIO0C2_SHIFT = 4,
57 GPIO0C2_MASK = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
58 GPIO0C2_GPIO = 0,
59 GPIO0C2_LCDC_D14 = (1 << GPIO0C2_SHIFT),
60 GPIO0C2_TRACE_D4 = (2 << GPIO0C2_SHIFT),
61 GPIO0C2_MCU_JTAG_TDI = (3 << GPIO0C2_SHIFT),
62
63 GPIO0C1_SHIFT = 2,
64 GPIO0C1_MASK = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT),
65 GPIO0C1_GPIO = 0,
66 GPIO0C1_LCDC_D13 = (1 << GPIO0C1_SHIFT),
67 GPIO0C1_TRACE_D3 = (2 << GPIO0C1_SHIFT),
68 GPIO0C1_MCU_JTAG_TRTSN = (3 << GPIO0C1_SHIFT),
69
70 GPIO0C0_SHIFT = 0,
71 GPIO0C0_MASK = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT),
72 GPIO0C0_GPIO = 0,
73 GPIO0C0_LCDC_D12 = (1 << GPIO0C0_SHIFT),
74 GPIO0C0_TRACE_D2 = (2 << GPIO0C0_SHIFT),
75 GPIO0C0_MCU_JTAG_TDO = (3 << GPIO0C0_SHIFT),
76};
77
78/*GRF_GPIO0D_IOMUX*/
79enum {
80 GPIO0D7_SHIFT = 14,
81 GPIO0D7_MASK = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT),
82 GPIO0D7_GPIO = 0,
83 GPIO0D7_LCDC_DCLK = (1 << GPIO0D7_SHIFT),
84 GPIO0D7_TRACE_CTL = (2 << GPIO0D7_SHIFT),
85 GPIO0D7_PMU_DEBUG5 = (3 << GPIO0D7_SHIFT),
86
87 GPIO0D6_SHIFT = 12,
88 GPIO0D6_MASK = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT),
89 GPIO0D6_GPIO = 0,
90 GPIO0D6_LCDC_DEN = (1 << GPIO0D6_SHIFT),
91 GPIO0D6_TRACE_CLK = (2 << GPIO0D6_SHIFT),
92 GPIO0D6_PMU_DEBUG4 = (3 << GPIO0D6_SHIFT),
93
94 GPIO0D5_SHIFT = 10,
95 GPIO0D5_MASK = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT),
96 GPIO0D5_GPIO = 0,
97 GPIO0D5_LCDC_VSYNC = (1 << GPIO0D5_SHIFT),
98 GPIO0D5_TRACE_D15 = (2 << GPIO0D5_SHIFT),
99 GPIO0D5_PMU_DEBUG3 = (3 << GPIO0D5_SHIFT),
100
101 GPIO0D4_SHIFT = 8,
102 GPIO0D4_MASK = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT),
103 GPIO0D4_GPIO = 0,
104 GPIO0D4_LCDC_HSYNC = (1 << GPIO0D4_SHIFT),
105 GPIO0D4_TRACE_D14 = (2 << GPIO0D4_SHIFT),
106 GPIO0D4_PMU_DEBUG2 = (3 << GPIO0D4_SHIFT),
107
108 GPIO0D3_SHIFT = 6,
109 GPIO0D3_MASK = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT),
110 GPIO0D3_GPIO = 0,
111 GPIO0D3_LCDC_D23 = (1 << GPIO0D3_SHIFT),
112 GPIO0D3_TRACE_D13 = (2 << GPIO0D3_SHIFT),
113 GPIO0D3_UART4_SIN = (3 << GPIO0D3_SHIFT),
114
115 GPIO0D2_SHIFT = 4,
116 GPIO0D2_MASK = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT),
117 GPIO0D2_GPIO = 0,
118 GPIO0D2_LCDC_D22 = (1 << GPIO0D2_SHIFT),
119 GPIO0D2_TRACE_D12 = (2 << GPIO0D2_SHIFT),
120 GPIO0D2_UART4_SOUT = (3 << GPIO0D2_SHIFT),
121
122 GPIO0D1_SHIFT = 2,
123 GPIO0D1_MASK = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT),
124 GPIO0D1_GPIO = 0,
125 GPIO0D1_LCDC_D21 = (1 << GPIO0D1_SHIFT),
126 GPIO0D1_TRACE_D11 = (2 << GPIO0D1_SHIFT),
127 GPIO0D1_UART4_RTSN = (3 << GPIO0D1_SHIFT),
128
129 GPIO0D0_SHIFT = 0,
130 GPIO0D0_MASK = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT),
131 GPIO0D0_GPIO = 0,
132 GPIO0D0_LCDC_D20 = (1 << GPIO0D0_SHIFT),
133 GPIO0D0_TRACE_D10 = (2 << GPIO0D0_SHIFT),
134 GPIO0D0_UART4_CTSN = (3 << GPIO0D0_SHIFT),
135};
136
137/*GRF_GPIO2A_IOMUX*/
138enum {
139 GPIO2A7_SHIFT = 14,
140 GPIO2A7_MASK = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT),
141 GPIO2A7_GPIO = 0,
142 GPIO2A7_SDMMC0_D2 = (1 << GPIO2A7_SHIFT),
143 GPIO2A7_JTAG_TCK = (2 << GPIO2A7_SHIFT),
144
145 GPIO2A6_SHIFT = 12,
146 GPIO2A6_MASK = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT),
147 GPIO2A6_GPIO = 0,
148 GPIO2A6_SDMMC0_D1 = (1 << GPIO2A6_SHIFT),
149 GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
150
151 GPIO2A5_SHIFT = 10,
152 GPIO2A5_MASK = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT),
153 GPIO2A5_GPIO = 0,
154 GPIO2A5_SDMMC0_D0 = (1 << GPIO2A5_SHIFT),
155 GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
156
157 GPIO2A4_SHIFT = 8,
158 GPIO2A4_MASK = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT),
159 GPIO2A4_GPIO = 0,
160 GPIO2A4_FLASH_DQS = (1 << GPIO2A4_SHIFT),
161 GPIO2A4_EMMC_CLKOUT = (2 << GPIO2A4_SHIFT),
162
163 GPIO2A3_SHIFT = 6,
164 GPIO2A3_MASK = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT),
165 GPIO2A3_GPIO = 0,
166 GPIO2A3_FLASH_CSN3 = (1 << GPIO2A3_SHIFT),
167 GPIO2A3_EMMC_RSTNOUT = (2 << GPIO2A3_SHIFT),
168
169 GPIO2A2_SHIFT = 4,
170 GPIO2A2_MASK = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT),
171 GPIO2A2_GPIO = 0,
172 GPIO2A2_FLASH_CSN2 = (1 << GPIO2A2_SHIFT),
173
174 GPIO2A1_SHIFT = 2,
175 GPIO2A1_MASK = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT),
176 GPIO2A1_GPIO = 0,
177 GPIO2A1_FLASH_CSN1 = (1 << GPIO2A1_SHIFT),
178
179 GPIO2A0_SHIFT = 0,
180 GPIO2A0_MASK = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT),
181 GPIO2A0_GPIO = 0,
182 GPIO2A0_FLASH_CSN0 = (1 << GPIO2A0_SHIFT),
183};
184
185/*GRF_GPIO2D_IOMUX*/
186enum {
187 GPIO2D7_SHIFT = 14,
188 GPIO2D7_MASK = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT),
189 GPIO2D7_GPIO = 0,
190 GPIO2D7_SDIO0_D3 = (1 << GPIO2D7_SHIFT),
191
192 GPIO2D6_SHIFT = 12,
193 GPIO2D6_MASK = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT),
194 GPIO2D6_GPIO = 0,
195 GPIO2D6_SDIO0_D2 = (1 << GPIO2D6_SHIFT),
196
197 GPIO2D5_SHIFT = 10,
198 GPIO2D5_MASK = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT),
199 GPIO2D5_GPIO = 0,
200 GPIO2D5_SDIO0_D1 = (1 << GPIO2D5_SHIFT),
201
202 GPIO2D4_SHIFT = 8,
203 GPIO2D4_MASK = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT),
204 GPIO2D4_GPIO = 0,
205 GPIO2D4_SDIO0_D0 = (1 << GPIO2D4_SHIFT),
206
207 GPIO2D3_SHIFT = 6,
208 GPIO2D3_MASK = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT),
209 GPIO2D3_GPIO = 0,
210 GPIO2D3_UART0_RTS0 = (1 << GPIO2D3_SHIFT),
211
212 GPIO2D2_SHIFT = 4,
213 GPIO2D2_MASK = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT),
214 GPIO2D2_GPIO = 0,
215 GPIO2D2_UART0_CTS0 = (1 << GPIO2D2_SHIFT),
216
217 GPIO2D1_SHIFT = 2,
218 GPIO2D1_MASK = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT),
219 GPIO2D1_GPIO = 0,
220 GPIO2D1_UART0_SOUT = (1 << GPIO2D1_SHIFT),
221
222 GPIO2D0_SHIFT = 0,
223 GPIO2D0_MASK = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT),
224 GPIO2D0_GPIO = 0,
225 GPIO2D0_UART0_SIN = (1 << GPIO2D0_SHIFT),
226};
227
228/* GRF_GPIO1C_IOMUX */
229enum {
230 GPIO1C7_SHIFT = 14,
231 GPIO1C7_MASK = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT),
232 GPIO1C7_GPIO = 0,
233 GPIO1C7_EMMC_DATA5 = (2 << GPIO1C7_SHIFT),
234
235 GPIO1C6_SHIFT = 12,
236 GPIO1C6_MASK = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT),
237 GPIO1C6_GPIO = 0,
238 GPIO1C6_EMMC_DATA4 = (2 << GPIO1C6_SHIFT),
239
240 GPIO1C5_SHIFT = 10,
241 GPIO1C5_MASK = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT),
242 GPIO1C5_GPIO = 0,
243 GPIO1C5_EMMC_DATA3 = (2 << GPIO1C5_SHIFT),
244
245 GPIO1C4_SHIFT = 8,
246 GPIO1C4_MASK = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT),
247 GPIO1C4_GPIO = 0,
248 GPIO1C4_EMMC_DATA2 = (2 << GPIO1C4_SHIFT),
249
250 GPIO1C3_SHIFT = 6,
251 GPIO1C3_MASK = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT),
252 GPIO1C3_GPIO = 0,
253 GPIO1C3_EMMC_DATA1 = (2 << GPIO1C3_SHIFT),
254
255 GPIO1C2_SHIFT = 4,
256 GPIO1C2_MASK = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT),
257 GPIO1C2_GPIO = 0,
258 GPIO1C2_EMMC_DATA0 = (2 << GPIO1C2_SHIFT),
259};
260
261/* GRF_GPIO1D_IOMUX*/
262enum {
263 GPIO1D3_SHIFT = 6,
264 GPIO1D3_MASK = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT),
265 GPIO1D3_GPIO = 0,
266 GPIO1D3_EMMC_PWREN = (2 << GPIO1D3_SHIFT),
267
268 GPIO1D2_SHIFT = 4,
269 GPIO1D2_MASK = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT),
270 GPIO1D2_GPIO = 0,
271 GPIO1D2_EMMC_CMD = (2 << GPIO1D2_SHIFT),
272
273 GPIO1D1_SHIFT = 2,
274 GPIO1D1_MASK = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT),
275 GPIO1D1_GPIO = 0,
276 GPIO1D1_EMMC_DATA7 = (2 << GPIO1D1_SHIFT),
277
278 GPIO1D0_SHIFT = 0,
279 GPIO1D0_MASK = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT),
280 GPIO1D0_GPIO = 0,
281 GPIO1D0_EMMC_DATA6 = (2 << GPIO1D0_SHIFT),
282};
283
284
285/*GRF_GPIO3B_IOMUX*/
286enum {
287 GPIO3B7_SHIFT = 14,
288 GPIO3B7_MASK = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT),
289 GPIO3B7_GPIO = 0,
290 GPIO3B7_MAC_RXD0 = (1 << GPIO3B7_SHIFT),
291
292 GPIO3B6_SHIFT = 12,
293 GPIO3B6_MASK = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT),
294 GPIO3B6_GPIO = 0,
295 GPIO3B6_MAC_TXD3 = (1 << GPIO3B6_SHIFT),
296
297 GPIO3B5_SHIFT = 10,
298 GPIO3B5_MASK = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT),
299 GPIO3B5_GPIO = 0,
300 GPIO3B5_MAC_TXEN = (1 << GPIO3B5_SHIFT),
301
302 GPIO3B4_SHIFT = 8,
303 GPIO3B4_MASK = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT),
304 GPIO3B4_GPIO = 0,
305 GPIO3B4_MAC_COL = (1 << GPIO3B4_SHIFT),
306
307 GPIO3B3_SHIFT = 6,
308 GPIO3B3_MASK = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT),
309 GPIO3B3_GPIO = 0,
310 GPIO3B3_MAC_CRS = (1 << GPIO3B3_SHIFT),
311
312 GPIO3B2_SHIFT = 4,
313 GPIO3B2_MASK = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT),
314 GPIO3B2_GPIO = 0,
315 GPIO3B2_MAC_TXD2 = (1 << GPIO3B2_SHIFT),
316
317 GPIO3B1_SHIFT = 2,
318 GPIO3B1_MASK = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT),
319 GPIO3B1_GPIO = 0,
320 GPIO3B1_MAC_TXD1 = (1 << GPIO3B1_SHIFT),
321
322 GPIO3B0_SHIFT = 0,
323 GPIO3B0_MASK = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT),
324 GPIO3B0_GPIO = 0,
325 GPIO3B0_MAC_TXD0 = (1 << GPIO3B0_SHIFT),
326 GPIO3B0_PWM0 = (2 << GPIO3B0_SHIFT),
327};
328
329/*GRF_GPIO3C_IOMUX*/
330enum {
331 GPIO3C6_SHIFT = 12,
332 GPIO3C6_MASK = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT),
333 GPIO3C6_GPIO = 0,
334 GPIO3C6_MAC_CLK = (1 << GPIO3C6_SHIFT),
335
336 GPIO3C5_SHIFT = 10,
337 GPIO3C5_MASK = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT),
338 GPIO3C5_GPIO = 0,
339 GPIO3C5_MAC_RXEN = (1 << GPIO3C5_SHIFT),
340
341 GPIO3C4_SHIFT = 8,
342 GPIO3C4_MASK = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT),
343 GPIO3C4_GPIO = 0,
344 GPIO3C4_MAC_RXDV = (1 << GPIO3C4_SHIFT),
345
346 GPIO3C3_SHIFT = 6,
347 GPIO3C3_MASK = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT),
348 GPIO3C3_GPIO = 0,
349 GPIO3C3_MAC_MDC = (1 << GPIO3C3_SHIFT),
350
351 GPIO3C2_SHIFT = 4,
352 GPIO3C2_MASK = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT),
353 GPIO3C2_GPIO = 0,
354 GPIO3C2_MAC_RXD3 = (1 << GPIO3C2_SHIFT),
355
356 GPIO3C1_SHIFT = 2,
357 GPIO3C1_MASK = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT),
358 GPIO3C1_GPIO = 0,
359 GPIO3C1_MAC_RXD2 = (1 << GPIO3C1_SHIFT),
360
361 GPIO3C0_SHIFT = 0,
362 GPIO3C0_MASK = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT),
363 GPIO3C0_GPIO = 0,
364 GPIO3C0_MAC_RXD1 = (1 << GPIO3C0_SHIFT),
365};
366
367/*GRF_GPIO3D_IOMUX*/
368enum {
369 GPIO3D4_SHIFT = 8,
370 GPIO3D4_MASK = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT),
371 GPIO3D4_GPIO = 0,
372 GPIO3D4_MAC_TXCLK = (1 << GPIO3D4_SHIFT),
373
374 GPIO3D1_SHIFT = 2,
375 GPIO3D1_MASK = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT),
376 GPIO3D1_GPIO = 0,
377 GPIO3D1_MAC_RXCLK = (1 << GPIO3D1_SHIFT),
378
379 GPIO3D0_SHIFT = 0,
380 GPIO3D0_MASK = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT),
381 GPIO3D0_GPIO = 0,
382 GPIO3D0_MAC_MDIO = (1 << GPIO3D0_SHIFT),
383};
384
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]385struct rk3368_pinctrl_priv {
386 struct rk3368_grf *grf;
387 struct rk3368_pmu_grf *pmugrf;
388};
389
390static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
391 int uart_id)
392{
393 struct rk3368_grf *grf = priv->grf;
394 struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
395
396 switch (uart_id) {
397 case PERIPH_ID_UART2:
398 rk_clrsetreg(&grf->gpio2a_iomux,
399 GPIO2A6_MASK | GPIO2A5_MASK,
Philipp Tomsich9ac1d832017-07-25 17:01:06 +0200[diff] [blame]400 GPIO2A6_UART2_SIN | GPIO2A5_UART2_SOUT);
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]401 break;
402 case PERIPH_ID_UART0:
403 break;
404 case PERIPH_ID_UART1:
405 break;
406 case PERIPH_ID_UART3:
407 break;
408 case PERIPH_ID_UART4:
409 rk_clrsetreg(&pmugrf->gpio0d_iomux,
410 GPIO0D0_MASK | GPIO0D1_MASK |
411 GPIO0D2_MASK | GPIO0D3_MASK,
Philipp Tomsich9ac1d832017-07-25 17:01:06 +0200[diff] [blame]412 GPIO0D0_GPIO | GPIO0D1_GPIO |
413 GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]414 break;
415 default:
416 debug("uart id = %d iomux error!\n", uart_id);
417 break;
418 }
419}
420
Philipp Tomsich34879432017-07-14 20:00:58 +0200[diff] [blame]421#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
422static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
423{
424 rk_clrsetreg(&grf->gpio3b_iomux,
425 GPIO3B0_MASK | GPIO3B1_MASK |
426 GPIO3B2_MASK | GPIO3B5_MASK |
427 GPIO3B6_MASK | GPIO3B7_MASK,
428 GPIO3B0_MAC_TXD0 | GPIO3B1_MAC_TXD1 |
429 GPIO3B2_MAC_TXD2 | GPIO3B5_MAC_TXEN |
430 GPIO3B6_MAC_TXD3 | GPIO3B7_MAC_RXD0);
431 rk_clrsetreg(&grf->gpio3c_iomux,
432 GPIO3C0_MASK | GPIO3C1_MASK |
433 GPIO3C2_MASK | GPIO3C3_MASK |
434 GPIO3C4_MASK | GPIO3C5_MASK |
435 GPIO3C6_MASK,
436 GPIO3C0_MAC_RXD1 | GPIO3C1_MAC_RXD2 |
437 GPIO3C2_MAC_RXD3 | GPIO3C3_MAC_MDC |
438 GPIO3C4_MAC_RXDV | GPIO3C5_MAC_RXEN |
439 GPIO3C6_MAC_CLK);
440 rk_clrsetreg(&grf->gpio3d_iomux,
441 GPIO3D0_MASK | GPIO3D1_MASK |
442 GPIO3D4_MASK,
443 GPIO3D0_MAC_MDIO | GPIO3D1_MAC_RXCLK |
444 GPIO3D4_MAC_TXCLK);
445}
446#endif
447
Philipp Tomsicha5e31132017-07-14 20:07:11 +0200[diff] [blame]448static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf, int mmc_id)
449{
450 switch (mmc_id) {
451 case PERIPH_ID_EMMC:
452 debug("mmc id = %d setting registers!\n", mmc_id);
453 rk_clrsetreg(&grf->gpio1c_iomux,
454 GPIO1C2_MASK | GPIO1C3_MASK |
455 GPIO1C4_MASK | GPIO1C5_MASK |
456 GPIO1C6_MASK | GPIO1C7_MASK,
457 GPIO1C2_EMMC_DATA0 |
458 GPIO1C3_EMMC_DATA1 |
459 GPIO1C4_EMMC_DATA2 |
460 GPIO1C5_EMMC_DATA3 |
461 GPIO1C6_EMMC_DATA4 |
462 GPIO1C7_EMMC_DATA5);
463 rk_clrsetreg(&grf->gpio1d_iomux,
464 GPIO1D0_MASK | GPIO1D1_MASK |
465 GPIO1D2_MASK | GPIO1D3_MASK,
466 GPIO1D0_EMMC_DATA6 |
467 GPIO1D1_EMMC_DATA7 |
468 GPIO1D2_EMMC_CMD |
469 GPIO1D3_EMMC_PWREN);
470 rk_clrsetreg(&grf->gpio2a_iomux,
471 GPIO2A3_MASK | GPIO2A4_MASK,
472 GPIO2A3_EMMC_RSTNOUT |
473 GPIO2A4_EMMC_CLKOUT);
474 break;
475 case PERIPH_ID_SDCARD:
476 /*
477 * We assume that the BROM has already set this up
478 * correctly for us and that there's nothing to do
479 * here.
480 */
481 break;
482 default:
483 debug("mmc id = %d iomux error!\n", mmc_id);
484 break;
485 }
486}
487
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]488static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
489{
490 struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
491
492 debug("%s: func=%d, flags=%x\n", __func__, func, flags);
493 switch (func) {
494 case PERIPH_ID_UART0:
495 case PERIPH_ID_UART1:
496 case PERIPH_ID_UART2:
497 case PERIPH_ID_UART3:
498 case PERIPH_ID_UART4:
499 pinctrl_rk3368_uart_config(priv, func);
500 break;
Philipp Tomsicha5e31132017-07-14 20:07:11 +0200[diff] [blame]501 case PERIPH_ID_EMMC:
502 case PERIPH_ID_SDCARD:
503 pinctrl_rk3368_sdmmc_config(priv->grf, func);
504 break;
Philipp Tomsich34879432017-07-14 20:00:58 +0200[diff] [blame]505#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
506 case PERIPH_ID_GMAC:
507 pinctrl_rk3368_gmac_config(priv->grf, func);
508 break;
509#endif
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]510 default:
511 return -EINVAL;
512 }
513
514 return 0;
515}
516
517static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
518 struct udevice *periph)
519{
520 u32 cell[3];
521 int ret;
522
523 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
524 "interrupts", cell, ARRAY_SIZE(cell));
525 if (ret < 0)
526 return -EINVAL;
527
528 switch (cell[1]) {
529 case 59:
530 return PERIPH_ID_UART4;
531 case 58:
532 return PERIPH_ID_UART3;
533 case 57:
534 return PERIPH_ID_UART2;
535 case 56:
536 return PERIPH_ID_UART1;
537 case 55:
538 return PERIPH_ID_UART0;
Philipp Tomsicha5e31132017-07-14 20:07:11 +0200[diff] [blame]539 case 35:
540 return PERIPH_ID_EMMC;
541 case 32:
542 return PERIPH_ID_SDCARD;
Philipp Tomsich34879432017-07-14 20:00:58 +0200[diff] [blame]543#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
544 case 27:
545 return PERIPH_ID_GMAC;
546#endif
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]547 }
548
549 return -ENOENT;
550}
551
552static int rk3368_pinctrl_set_state_simple(struct udevice *dev,
553 struct udevice *periph)
554{
555 int func;
556
557 func = rk3368_pinctrl_get_periph_id(dev, periph);
558 if (func < 0)
559 return func;
560
561 return rk3368_pinctrl_request(dev, func, 0);
562}
563
564static struct pinctrl_ops rk3368_pinctrl_ops = {
565 .set_state_simple = rk3368_pinctrl_set_state_simple,
566 .request = rk3368_pinctrl_request,
567 .get_periph_id = rk3368_pinctrl_get_periph_id,
568};
569
570static int rk3368_pinctrl_probe(struct udevice *dev)
571{
572 struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
573 int ret = 0;
574
575 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
576 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
577
578 debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf);
579
580 return ret;
581}
582
583static const struct udevice_id rk3368_pinctrl_ids[] = {
584 { .compatible = "rockchip,rk3368-pinctrl" },
585 { }
586};
587
588U_BOOT_DRIVER(pinctrl_rk3368) = {
589 .name = "rockchip_rk3368_pinctrl",
590 .id = UCLASS_PINCTRL,
591 .of_match = rk3368_pinctrl_ids,
592 .priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv),
593 .ops = &rk3368_pinctrl_ops,
594 .bind = dm_scan_fdt_dev,
595 .probe = rk3368_pinctrl_probe,
596};