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Andy Yanb5e16302019-11-14 11:21:12 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef __CONFIG_RK3308_COMMON_H
7#define __CONFIG_RK3308_COMMON_H
8
9#include "rockchip-common.h"
10
11#define CONFIG_SYS_CBSIZE 1024
Andy Yanb5e16302019-11-14 11:21:12 +080012#define CONFIG_SPL_MAX_SIZE 0x20000
13#define CONFIG_SPL_BSS_START_ADDR 0x00400000
14#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
Andy Yanb5e16302019-11-14 11:21:12 +080015
16#define CONFIG_SYS_NS16550_MEM32
17
Andy Yanb5e16302019-11-14 11:21:12 +080018#define CONFIG_IRAM_BASE 0xfff80000
19#define CONFIG_SYS_INIT_SP_ADDR 0x00800000
Andy Yanb5e16302019-11-14 11:21:12 +080020#define CONFIG_SPL_STACK 0x00400000
21#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
22
23#define COUNTER_FREQUENCY 24000000
24
25#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
26
27#define CONFIG_SYS_SDRAM_BASE 0
28#define SDRAM_MAX_SIZE 0xff000000
29#define SDRAM_BANK_SIZE (2UL << 30)
30
31#ifndef CONFIG_SPL_BUILD
32
33#define ENV_MEM_LAYOUT_SETTINGS \
34 "scriptaddr=0x00500000\0" \
35 "pxefile_addr_r=0x00600000\0" \
Andy Yan038626e2019-12-26 15:20:04 +080036 "fdt_addr_r=0x02800000\0" \
Andy Yanb5e16302019-11-14 11:21:12 +080037 "kernel_addr_r=0x00680000\0" \
38 "ramdisk_addr_r=0x04000000\0"
39
40#include <config_distro_bootcmd.h>
41#define CONFIG_EXTRA_ENV_SETTINGS \
42 ENV_MEM_LAYOUT_SETTINGS \
43 "partitions=" PARTS_DEFAULT \
44 ROCKCHIP_DEVICE_SETTINGS \
45 BOOTENV
46
47#endif
48
49#endif