blob: ce6afcde2a012edf8fc8fb5dbe4fae9cc471722c [file] [log] [blame]
Fabio Estevamebc8fcc2019-12-09 10:43:03 -03001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 *
5 * Configuration settings for the Embedded Artists i.MX7ULP COM board.
6 */
7
8#ifndef __MX7ULP_COM_CONFIG_H
9#define __MX7ULP_COM_CONFIG_H
10
11#include <linux/sizes.h>
12#include <asm/arch/imx-regs.h>
13
Ricardo Salveti02192502021-09-12 17:32:57 +030014#ifdef CONFIG_SPL
15#include "imx7ulp_spl.h"
16#endif
17
Fabio Estevamebc8fcc2019-12-09 10:43:03 -030018#define CONFIG_SYS_BOOTM_LEN 0x1000000
19
Fabio Estevamebc8fcc2019-12-09 10:43:03 -030020#define CONFIG_MMCROOT "/dev/mmcblk0p2"
Fabio Estevamebc8fcc2019-12-09 10:43:03 -030021
22/* Using ULP WDOG for reset */
23#define WDOG_BASE_ADDR WDG1_RBASE
24
25#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */
26
Fabio Estevamebc8fcc2019-12-09 10:43:03 -030027/* UART */
28#define LPUART_BASE LPUART4_RBASE
29
Fabio Estevamebc8fcc2019-12-09 10:43:03 -030030/* Physical Memory Map */
31
32#define PHYS_SDRAM 0x60000000
Fabio Estevamebc8fcc2019-12-09 10:43:03 -030033#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
34
Fabio Estevamebc8fcc2019-12-09 10:43:03 -030035#define CONFIG_EXTRA_ENV_SETTINGS \
36 "image=zImage\0" \
37 "console=ttyLP0\0" \
38 "fdt_high=0xffffffff\0" \
39 "initrd_high=0xffffffff\0" \
40 "fdt_file=imx7ulp-com.dtb\0" \
41 "fdt_addr=0x63000000\0" \
42 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
Tom Rinib113bca2021-12-11 14:55:52 -050043 "mmcpart=1\0" \
Fabio Estevamebc8fcc2019-12-09 10:43:03 -030044 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
45 "mmcargs=setenv bootargs console=${console},${baudrate} " \
46 "root=${mmcroot}\0" \
47 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
48 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
49 "mmcboot=echo Booting from mmc ...; " \
50 "run mmcargs; " \
51 "if run loadfdt; then " \
52 "bootz ${loadaddr} - ${fdt_addr}; " \
53 "fi;\0" \
54
Fabio Estevamebc8fcc2019-12-09 10:43:03 -030055#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
56#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
57
58#define CONFIG_SYS_INIT_SP_OFFSET \
59 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
60#define CONFIG_SYS_INIT_SP_ADDR \
61 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
62
Fabio Estevamebc8fcc2019-12-09 10:43:03 -030063#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
64#endif /* __CONFIG_H */