| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007-2008 |
| Stelian Pop | 5ee0c7f | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 4 | * Stelian Pop <stelian@popies.net> |
| Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 5 | * Lead Tech Design <www.leadtechdesign.com> |
| 6 | * |
| 7 | * Configuation settings for the AT91SAM9RLEK board. |
| Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
| Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 13 | #include <asm/hardware.h> |
| 14 | |
| Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 15 | /* ARM asynchronous clock */ |
| Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 16 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
| 17 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ |
| Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 18 | |
| Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 19 | /* |
| 20 | * Hardware drivers |
| 21 | */ |
| Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 22 | |
| Stelian Pop | cea5c53 | 2008-05-08 14:52:32 +0200 | [diff] [blame] | 23 | /* LCD */ |
| Stelian Pop | cea5c53 | 2008-05-08 14:52:32 +0200 | [diff] [blame] | 24 | #define LCD_BPP LCD_COLOR8 |
| Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 25 | /* Let board_init_f handle the framebuffer allocation */ |
| 26 | #undef CONFIG_FB_ADDR |
| Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 27 | |
| Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 28 | /* SDRAM */ |
| Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 29 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
| 30 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 |
| 31 | |
| 32 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| Wenyou Yang | 3cbbeb1 | 2017-04-18 15:28:27 +0800 | [diff] [blame] | 33 | (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
| Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 34 | |
| Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 35 | /* NAND flash */ |
| Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 36 | #ifdef CONFIG_CMD_NAND |
| Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 37 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 38 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
| Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 39 | #define CONFIG_SYS_NAND_DBW_8 1 |
| Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 40 | /* our ALE is AD21 */ |
| 41 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 42 | /* our CLE is AD22 */ |
| 43 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
| 44 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6 |
| 45 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17 |
| Wolfgang Denk | 1f79774 | 2009-07-18 21:52:24 +0200 | [diff] [blame] | 46 | |
| Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 47 | #endif |
| Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 48 | |
| Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 49 | #endif |