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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek952d5142007-03-11 13:42:58 +01002/*
3 * (C) Copyright 2007 Michal Simek
4 *
5 * Michal SIMEK <monstr@monstr.eu>
Michal Simek952d5142007-03-11 13:42:58 +01006 */
7
Shreenidhi Shediffced402018-07-15 02:34:35 +05308/*
9 * This is a board specific file. It's OK to include board specific
10 * header files
11 */
Michal Simek952d5142007-03-11 13:42:58 +010012
13#include <common.h>
Michal Simekdda9bd82007-03-30 22:52:09 +020014#include <config.h>
Michal Simek65e915c2014-05-08 16:08:44 +020015#include <fdtdec.h>
Michal Simek9cabb362012-07-04 13:12:37 +020016#include <asm/processor.h>
Michal Simek9c817f82007-05-07 19:33:51 +020017#include <asm/microblaze_intc.h>
18#include <asm/asm.h>
Michal Simek23ccda02013-04-24 10:01:20 +020019#include <asm/gpio.h>
Shreenidhi Shedi1f8fcbb2018-07-15 02:05:40 +053020#include <dm/uclass.h>
21#include <wdt.h>
Michal Simek23ccda02013-04-24 10:01:20 +020022
Michal Simek65e915c2014-05-08 16:08:44 +020023DECLARE_GLOBAL_DATA_PTR;
24
Michal Simek23ccda02013-04-24 10:01:20 +020025#ifdef CONFIG_XILINX_GPIO
26static int reset_pin = -1;
27#endif
Michal Simek952d5142007-03-11 13:42:58 +010028
Shreenidhi Shedi1f8fcbb2018-07-15 02:05:40 +053029#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
30static struct udevice *watchdog_dev;
31#endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */
32
Michal Simek65e915c2014-05-08 16:08:44 +020033ulong ram_base;
34
Simon Glass2f949c32017-03-31 08:40:32 -060035int dram_init_banksize(void)
Michal Simek65e915c2014-05-08 16:08:44 +020036{
37 gd->bd->bi_dram[0].start = ram_base;
38 gd->bd->bi_dram[0].size = get_effective_memsize();
Simon Glass2f949c32017-03-31 08:40:32 -060039
40 return 0;
Michal Simek65e915c2014-05-08 16:08:44 +020041}
42
43int dram_init(void)
44{
45 int node;
46 fdt_addr_t addr;
47 fdt_size_t size;
48 const void *blob = gd->fdt_blob;
49
50 node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
51 "memory", 7);
52 if (node == -FDT_ERR_NOTFOUND) {
53 debug("DRAM: Can't get memory node\n");
54 return 1;
55 }
56 addr = fdtdec_get_addr_size(blob, node, "reg", &size);
57 if (addr == FDT_ADDR_T_NONE || size == 0) {
58 debug("DRAM: Can't get base address or size\n");
59 return 1;
60 }
61 ram_base = addr;
62
63 gd->ram_top = addr; /* In setup_dest_addr() is done +ram_size */
64 gd->ram_size = size;
65
66 return 0;
67};
Michal Simek65e915c2014-05-08 16:08:44 +020068
Michal Simekcda7d202018-06-28 10:30:05 +020069#if !defined(CONFIG_SYSRESET) || defined(CONFIG_SPL_BUILD)
Mike Frysinger6d1f6982010-10-20 03:41:17 -040070int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Michal Simek952d5142007-03-11 13:42:58 +010071{
Michal Simek8cd24912015-12-09 11:53:25 +010072#ifndef CONFIG_SPL_BUILD
Michal Simek23ccda02013-04-24 10:01:20 +020073#ifdef CONFIG_XILINX_GPIO
74 if (reset_pin != -1)
75 gpio_direction_output(reset_pin, 1);
Michal Simek952d5142007-03-11 13:42:58 +010076#endif
Michal Simek8cd24912015-12-09 11:53:25 +010077#endif
Shreenidhi Shediffced402018-07-15 02:34:35 +053078 puts("Resetting board\n");
Michal Simekc9446872012-11-07 15:27:39 +010079 __asm__ __volatile__ (" mts rmsr, r0;" \
80 "bra r0");
Michal Simek25d20af2012-11-02 09:33:05 +010081
Mike Frysinger6d1f6982010-10-20 03:41:17 -040082 return 0;
Michal Simek952d5142007-03-11 13:42:58 +010083}
Michal Simekcda7d202018-06-28 10:30:05 +020084#endif
Michal Simek952d5142007-03-11 13:42:58 +010085
Michal Simek01525242015-12-11 15:01:28 +010086static int gpio_init(void)
Michal Simek952d5142007-03-11 13:42:58 +010087{
Michal Simek23ccda02013-04-24 10:01:20 +020088#ifdef CONFIG_XILINX_GPIO
89 reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
90 if (reset_pin != -1)
91 gpio_request(reset_pin, "reset_pin");
Michal Simek952d5142007-03-11 13:42:58 +010092#endif
93 return 0;
94}
Shreenidhi Shedi1f8fcbb2018-07-15 02:05:40 +053095
96#ifdef CONFIG_WDT
97/* Called by macro WATCHDOG_RESET */
98void watchdog_reset(void)
99{
100#if !defined(CONFIG_SPL_BUILD)
101 ulong now;
102 static ulong next_reset;
103
104 if (!watchdog_dev)
105 return;
106
107 now = timer_get_us();
108
109 /* Do not reset the watchdog too often */
110 if (now > next_reset) {
111 wdt_reset(watchdog_dev);
112 next_reset = now + 1000;
113 }
114#endif /* !CONFIG_SPL_BUILD */
115}
116#endif /* CONFIG_WDT */
Michal Simek9c817f82007-05-07 19:33:51 +0200117
Michal Simek01525242015-12-11 15:01:28 +0100118int board_late_init(void)
Michal Simek9cabb362012-07-04 13:12:37 +0200119{
120 gpio_init();
Michal Simek01525242015-12-11 15:01:28 +0100121
Shreenidhi Shedi1f8fcbb2018-07-15 02:05:40 +0530122#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
123 watchdog_dev = NULL;
124
125 if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
126 debug("Watchdog: Not found by seq!\n");
127 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
128 puts("Watchdog: Not found!\n");
129 return 0;
130 }
131 }
132
133 wdt_start(watchdog_dev, 0, 0);
134 puts("Watchdog: Started\n");
135#endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */
136
Michal Simek01525242015-12-11 15:01:28 +0100137 return 0;
Michal Simek9cabb362012-07-04 13:12:37 +0200138}