| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Marcel Ziswiler | 11e2a53 | 2014-09-05 10:18:38 +0200 | [diff] [blame] | 2 | /* |
| Marcel Ziswiler | d92dee5 | 2016-11-16 17:49:23 +0100 | [diff] [blame] | 3 | * Copyright (c) 2014-2016 Marcel Ziswiler |
| Marcel Ziswiler | 11e2a53 | 2014-09-05 10:18:38 +0200 | [diff] [blame] | 4 | * |
| Marcel Ziswiler | 764d412 | 2015-08-06 00:47:10 +0200 | [diff] [blame] | 5 | * Configuration settings for the Toradex Apalis T30 modules. |
| Marcel Ziswiler | 11e2a53 | 2014-09-05 10:18:38 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
| 11 | #include <linux/sizes.h> |
| 12 | |
| 13 | #include "tegra30-common.h" |
| 14 | |
| Marcel Ziswiler | d6cd15f | 2019-09-12 11:12:55 +0200 | [diff] [blame] | 15 | /* |
| 16 | * Board-specific serial config |
| 17 | * |
| 18 | * Apalis UART1: NVIDIA UARTA |
| 19 | * Apalis UART2: NVIDIA UARTD |
| 20 | * Apalis UART3: NVIDIA UARTB |
| 21 | * Apalis UART4: NVIDIA UARTC |
| 22 | */ |
| Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 23 | #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE |
| Marcel Ziswiler | 11e2a53 | 2014-09-05 10:18:38 +0200 | [diff] [blame] | 24 | |
| Marcel Ziswiler | 11e2a53 | 2014-09-05 10:18:38 +0200 | [diff] [blame] | 25 | #include "tegra-common-post.h" |
| 26 | |
| 27 | #endif /* __CONFIG_H */ |