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git01.mediatek.com / filogic / uboot / 4ca60199d782c0f49a91e563594ea075379eab38 / . / arch / arm / dts / k2g.dtsi
blob: 88b1a8e998ac27e51ff479e90762859ff3e8ff6b [file] [log] [blame]
Lokesh Vutlae8e92b82015-09-19 16:26:55 +0530[diff] [blame]1/*
2 * Copyright 2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Galileo soc device tree
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include "skeleton.dtsi"
13
14/ {
15 model = "Texas Instruments Keystone 2 SoC";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 interrupt-parent = <&gic>;
19
20 aliases {
21 serial0 = &uart0;
Vignesh Rcefb8f32016-07-06 09:59:05 +0530[diff] [blame]22 spi0 = &spi0;
23 spi1 = &spi1;
24 spi2 = &spi2;
25 spi3 = &spi3;
Lokesh Vutlae8e92b82015-09-19 16:26:55 +0530[diff] [blame]26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0x80000000 0x80000000>;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 interrupt-parent = <&gic>;
38
39 cpu@0 {
40 compatible = "arm,cortex-a15";
41 device_type = "cpu";
42 reg = <0>;
43 };
44 };
45
46 gic: interrupt-controller {
47 compatible = "arm,cortex-a15-gic";
48 #interrupt-cells = <3>;
49 interrupt-controller;
50 reg = <0x0 0x02561000 0x0 0x1000>,
51 <0x0 0x02562000 0x0 0x2000>,
52 <0x0 0x02564000 0x0 0x1000>,
53 <0x0 0x02566000 0x0 0x2000>;
54 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
55 IRQ_TYPE_LEVEL_HIGH)>;
56 };
57
58 soc {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "ti,keystone","simple-bus";
62 interrupt-parent = <&gic>;
63 ranges;
64
65 uart0: serial@02530c00 {
66 compatible = "ns16550a";
67 current-speed = <115200>;
68 reg-shift = <2>;
69 reg-io-width = <4>;
70 reg = <0x02530c00 0x100>;
71 clock-names = "uart";
72 interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
73 };
74
Mugunthan V N3784cc22016-02-02 15:51:37 +0530[diff] [blame]75 mdio: mdio@4200f00 {
76 compatible = "ti,keystone_mdio", "ti,davinci_mdio";
77 #address-cells = <1>;
78 #size-cells = <0>;
79 /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
80 /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
81 clock-names = "fck";
82 reg = <0x04200f00 0x100>;
83 status = "disabled";
84 bus_freq = <2500000>;
85 };
86
87 #include "k2g-netcp.dtsi"
Nishanth Menon715137c2016-02-25 12:53:46 -0600[diff] [blame]88
89 pmmc: pmmc@2900000 {
90 compatible = "ti,power-processor";
91 reg = <0x02900000 0x40000>;
92 ti,lpsc_module = <1>;
93 };
94
Vignesh Rcefb8f32016-07-06 09:59:05 +0530[diff] [blame]95 spi0: spi@21805400 {
96 compatible = "ti,keystone-spi", "ti,dm6441-spi";
97 reg = <0x21805400 0x200>;
98 num-cs = <4>;
99 ti,davinci-spi-intr-line = <0>;
100 interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
101 #address-cells = <1>;
102 #size-cells = <0>;
103 status = "disabled";
104 };
105
106 spi1: spi@21805800 {
107 compatible = "ti,keystone-spi", "ti,dm6441-spi";
108 reg = <0x21805800 0x200>;
109 num-cs = <4>;
110 ti,davinci-spi-intr-line = <0>;
111 interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>;
112 #address-cells = <1>;
113 #size-cells = <0>;
114 status = "disabled";
115 };
116
117 spi2: spi@21805c00 {
118 compatible = "ti,keystone-spi", "ti,dm6441-spi";
119 reg = <0x21805C00 0x200>;
120 num-cs = <4>;
121 ti,davinci-spi-intr-line = <0>;
122 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
123 #address-cells = <1>;
124 #size-cells = <0>;
125 status = "disabled";
126 };
127
128 spi3: spi@21806000 {
129 compatible = "ti,keystone-spi", "ti,dm6441-spi";
130 reg = <0x21806000 0x200>;
131 num-cs = <4>;
132 ti,davinci-spi-intr-line = <0>;
133 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 status = "disabled";
137 };
Lokesh Vutlae8e92b82015-09-19 16:26:55 +0530[diff] [blame]138 };
139};