blob: 4918bf8f567184ca1efae2cdfcb284c2d239c37c [file] [log] [blame]
Anatolij Gustschin49234a32020-01-07 16:37:42 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2017 NXP
4 *
5 * Copyright 2019 Siemens AG
6 *
7 */
8
9/dts-v1/;
10
11#include "fsl-imx8qxp.dtsi"
Enrico Leto8eb67e62024-11-23 17:52:50 +010012#include "imx8-capricorn-u-boot.dtsi"
Anatolij Gustschin49234a32020-01-07 16:37:42 +010013
14/ {
Anatolij Gustschin49234a32020-01-07 16:37:42 +010015 chosen {
16 bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
17 stdout-path = &lpuart2;
18 };
19
Anatolij Gustschin49234a32020-01-07 16:37:42 +010020};
21
22&iomuxc {
23 pinctrl-names = "default";
24
25 muxcgrp: imx8qxp-som {
Anatolij Gustschin49234a32020-01-07 16:37:42 +010026 pinctrl_lpi2c0: lpi2c0grp {
27 fsl,pins = <
28 SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020
29 SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x0C000020
30 >;
31 };
32
33 pinctrl_lpi2c1: lpi2c1grp {
34 fsl,pins = <
35 SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x0C000020
36 SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x0C000020
37 >;
38 };
39
40 pinctrl_lpuart2: lpuart2grp {
41 fsl,pins = <
42 SC_P_UART2_RX_ADMA_UART2_RX 0x06000020
43 SC_P_UART2_TX_ADMA_UART2_TX 0x06000020
44 >;
45 };
46
47 pinctrl_usdhc1: usdhc1grp {
48 fsl,pins = <
49 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
50 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
51 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
52 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
53 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
54 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
55 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
56 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
57 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
58 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
59 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
60 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
61 SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021
62 >;
63 };
64
65 pinctrl_usdhc2: usdhc2grp {
66 fsl,pins = <
67 SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
68 SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
69 SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
70 SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
71 SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
72 SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
73 SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021
74 //SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021
75 SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021
76 >;
77 };
78
79 pinctrl_fec2: fec2grp {
80 fsl,pins = <
81 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
82 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
83 SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
84
85 SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060
86 SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060
87
88 SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060
89 SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
90 SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
91 SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060
92 SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
93 SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
94 SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
95 SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */
96 >;
97 };
98 };
99};
100
101&i2c0 {
102 clock-frequency = <100000>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_lpi2c0>;
105 status = "okay";
106};
107
108&i2c1 {
109 clock-frequency = <100000>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_lpi2c1>;
112 status = "okay";
113};
114
115&lpuart2 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_lpuart2>;
118 status = "okay";
119};
120
121&usdhc1 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_usdhc1>;
124 clock-frequency=<52000000>;
125 no-1-8-v;
126 bus-width = <8>;
127 non-removable;
128 status = "okay";
129};
130
131&gpio0 {
132 status = "okay";
133};
134
135&gpio1 {
136 status = "okay";
137};
138
139&gpio2 {
140 status = "okay";
141};
142
143&gpio3 {
144 status = "okay";
145};
146
147&gpio4 {
148 status = "okay";
149};
150
151&gpio5 {
152 status = "okay";
153};
154
155&fec1 {
156 status ="disabled";
157};
158
159&fec2 {
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_fec2>;
162 phy-mode = "rmii";
163
164 phy-handle = <&ethphy1>;
165 fsl,magic-packet;
166 status = "okay";
167
168 mdio {
169 #address-cells = <1>;
170 #size-cells = <0>;
171
172 ethphy0: ethernet-phy@0 {
173 compatible = "ethernet-phy-ieee802.3-c22";
174 reg = <0>;
175 };
176 ethphy1: ethernet-phy@1 {
177 compatible = "ethernet-phy-ieee802.3-c22";
178 reg = <1>;
179 };
180 };
181};