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Jason Liudec11122011-11-25 00:18:02 +00001/*
2 * (C) Copyright 2009
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Jason Liudec11122011-11-25 00:18:02 +00006 */
7
8#ifndef __ASM_ARCH_CLOCK_H
9#define __ASM_ARCH_CLOCK_H
10
Benoît Thébaudeauafac1652012-09-27 10:19:58 +000011#include <common.h>
12
13#ifdef CONFIG_SYS_MX6_HCLK
14#define MXC_HCLK CONFIG_SYS_MX6_HCLK
15#else
16#define MXC_HCLK 24000000
17#endif
18
19#ifdef CONFIG_SYS_MX6_CLK32
20#define MXC_CLK32 CONFIG_SYS_MX6_CLK32
21#else
22#define MXC_CLK32 32768
23#endif
24
Jason Liudec11122011-11-25 00:18:02 +000025enum mxc_clock {
26 MXC_ARM_CLK = 0,
27 MXC_PER_CLK,
28 MXC_AHB_CLK,
29 MXC_IPG_CLK,
30 MXC_IPG_PERCLK,
31 MXC_UART_CLK,
32 MXC_CSPI_CLK,
33 MXC_AXI_CLK,
34 MXC_EMI_SLOW_CLK,
35 MXC_DDR_CLK,
36 MXC_ESDHC_CLK,
37 MXC_ESDHC2_CLK,
38 MXC_ESDHC3_CLK,
39 MXC_ESDHC4_CLK,
40 MXC_SATA_CLK,
41 MXC_NFC_CLK,
Matthias Weisser99ba3422012-09-24 02:46:53 +000042 MXC_I2C_CLK,
Jason Liudec11122011-11-25 00:18:02 +000043};
44
Akshay Bhat4e364e62016-04-12 18:13:56 -040045enum ldb_di_clock {
46 MXC_PLL5_CLK = 0,
47 MXC_PLL2_PFD0_CLK,
48 MXC_PLL2_PFD2_CLK,
49 MXC_MMDC_CH1_CLK,
50 MXC_PLL3_SW_CLK,
51};
52
Fabio Estevamb2903ae2014-01-03 15:55:57 -020053enum enet_freq {
Stefan Roesed7e07312014-11-27 13:46:43 +010054 ENET_25MHZ,
55 ENET_50MHZ,
56 ENET_100MHZ,
57 ENET_125MHZ,
Fabio Estevamb2903ae2014-01-03 15:55:57 -020058};
59
Jason Liudec11122011-11-25 00:18:02 +000060u32 imx_get_uartclk(void);
61u32 imx_get_fecclk(void);
62unsigned int mxc_get_clock(enum mxc_clock clk);
Nikita Kiryanov98b76b42014-08-20 15:08:49 +030063void setup_gpmi_io_clk(u32 cfg);
Nitin Gargb1ce7012014-09-16 13:33:25 -050064void hab_caam_clock_enable(unsigned char enable);
Benoît Thébaudeau20db6312013-04-23 10:17:44 +000065void enable_ocotp_clk(unsigned char enable);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000066void enable_usboh3_clk(unsigned char enable);
Nikita Kiryanov98b76b42014-08-20 15:08:49 +030067void enable_uart_clk(unsigned char enable);
Nikita Kiryanov98b76b42014-08-20 15:08:49 +030068int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
Eric Nelsonfdba0762012-03-27 09:52:21 +000069int enable_sata_clock(void);
Nikita Kiryanov63659b72014-11-21 12:47:22 +020070void disable_sata_clock(void);
Marek Vasut563dfb22013-12-14 06:27:26 +010071int enable_pcie_clock(void);
Troy Kiskyd4fdc992012-07-19 08:18:25 +000072int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
Heiko Schocher472a68f2014-07-18 06:07:20 +020073int enable_spi_clk(unsigned char enable, unsigned spi_num);
Pardeep Kumar Singlac1fa1302013-07-25 12:12:13 -050074void enable_ipu_clock(void);
Peng Fan967a83b2015-08-12 17:46:50 +080075int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
Nikita Kiryanov98b76b42014-08-20 15:08:49 +030076void enable_enet_clk(unsigned char enable);
Peng Fan53ebda82015-10-29 15:54:47 +080077int enable_lcdif_clock(u32 base_addr);
Peng Fan828e4682014-12-31 11:01:38 +080078void enable_qspi_clk(int qspi_num);
Nitin Garg59f3be32014-11-20 21:14:12 +080079void enable_thermal_clk(void);
Peng Fan53ebda82015-10-29 15:54:47 +080080void mxs_set_lcdclk(u32 base_addr, u32 freq);
Akshay Bhat4e364e62016-04-12 18:13:56 -040081void select_ldb_di_clock_source(enum ldb_di_clock clk);
Lukasz Majewski529498e2016-11-28 07:18:14 +010082void enable_eim_clk(unsigned char enable);
Jason Liudec11122011-11-25 00:18:02 +000083#endif /* __ASM_ARCH_CLOCK_H */