blob: c3d97858d7f30c39b6f6f63c22504b1015e5a0bf [file] [log] [blame]
Michal Simek71d84b42018-03-27 13:43:05 +02001// SPDX-License-Identifier: GPL-2.0+
Peter Crosthwaite9d7740a2014-08-28 21:16:39 +10002/*
Michal Simeke2612e12015-07-22 11:12:10 +02003 * Copyright (C) 2011 - 2015 Xilinx
4 * Copyright (C) 2012 National Instruments Corp.
Peter Crosthwaite9d7740a2014-08-28 21:16:39 +10005 */
6/dts-v1/;
7#include "zynq-7000.dtsi"
8
9/ {
Luis Aranedaac891162018-07-12 00:10:20 -040010 model = "Digilent Zybo board";
Michal Simeke2612e12015-07-22 11:12:10 +020011 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
Peter Crosthwaite9d7740a2014-08-28 21:16:39 +100012
13 aliases {
Michal Simeke2612e12015-07-22 11:12:10 +020014 ethernet0 = &gem0;
Peter Crosthwaite9d7740a2014-08-28 21:16:39 +100015 serial0 = &uart1;
Nathan Rossib13bb072015-12-09 00:44:42 +100016 spi0 = &qspi;
Michal Simek1a03a522015-12-08 11:56:23 +010017 mmc0 = &sdhci0;
Peter Crosthwaite9d7740a2014-08-28 21:16:39 +100018 };
19
Michal Simekb3585f42016-11-11 13:11:37 +010020 memory@0 {
Peter Crosthwaite9d7740a2014-08-28 21:16:39 +100021 device_type = "memory";
Michal Simeke2612e12015-07-22 11:12:10 +020022 reg = <0x0 0x20000000>;
Peter Crosthwaite9d7740a2014-08-28 21:16:39 +100023 };
Michal Simeke2612e12015-07-22 11:12:10 +020024
25 chosen {
Michal Simek8073b862016-04-07 11:15:00 +020026 bootargs = "";
Michal Simeke2612e12015-07-22 11:12:10 +020027 stdout-path = "serial0:115200n8";
28 };
29
Nathan Rossib13bb072015-12-09 00:44:42 +100030 usb_phy0: phy0 {
Michal Simekb46e95f2016-04-07 14:42:53 +020031 #phy-cells = <0>;
Michal Simekd69a70e2017-11-02 09:24:12 +010032 compatible = "usb-nop-xceiv";
Michal Simek18d0fa12016-02-13 10:38:08 +010033 reset-gpios = <&gpio0 46 1>;
Nathan Rossib13bb072015-12-09 00:44:42 +100034 };
Michal Simeke2612e12015-07-22 11:12:10 +020035};
36
37&clkc {
38 ps-clk-frequency = <50000000>;
39};
40
41&gem0 {
42 status = "okay";
43 phy-mode = "rgmii-id";
44 phy-handle = <&ethernet_phy>;
45
46 ethernet_phy: ethernet-phy@0 {
47 reg = <0>;
48 };
49};
50
Michal Simek6603e1c2016-04-07 13:04:15 +020051&qspi {
Simon Glassd3a98cb2023-02-13 08:56:33 -070052 bootph-all;
Michal Simeke2612e12015-07-22 11:12:10 +020053 status = "okay";
54};
55
Michal Simek6603e1c2016-04-07 13:04:15 +020056&sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070057 bootph-all;
Michal Simeke2612e12015-07-22 11:12:10 +020058 status = "okay";
Nathan Rossib13bb072015-12-09 00:44:42 +100059};
60
Michal Simek6603e1c2016-04-07 13:04:15 +020061&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070062 bootph-all;
Nathan Rossib13bb072015-12-09 00:44:42 +100063 status = "okay";
64};
65
66&usb0 {
67 status = "okay";
68 dr_mode = "host";
69 usb-phy = <&usb_phy0>;
Peter Crosthwaite9d7740a2014-08-28 21:16:39 +100070};