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git01.mediatek.com / filogic / uboot / 4a4ebe308448b62123703d49355feffe3f9b1590 / . / arch / arm / dts / stm32mp157a-icore-stm32mp1-u-boot.dtsi
blob: 630c96efd085937fa579fec8fcc90e4e92c7abbf [file] [log] [blame]
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
4 * Copyright (c) 2020 Amarula Solutions(India)
5 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 */
7
8#include <dt-bindings/clock/stm32mp1-clksrc.h>
9#include "stm32mp15-u-boot.dtsi"
10#include "stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi"
11
12&vddcore {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]13 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]14};
15
16&vdd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]18};
19
20&vdd_usb {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]22};
23
24&vdda {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]26};
27
28&vdd_ddr {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]30};
31
32&vtt_ddr {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]34};
35
36&vref_ddr {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]38};
39
40&vdd_sd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]42};
43
44&v3v3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]46};
47
48&v2v8 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]50};
51
52&v1v8 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]54};
55
56&rcc {
57 st,clksrc = <
58 CLK_MPU_PLL1P
59 CLK_AXI_PLL2P
60 CLK_MCU_PLL3P
61 CLK_PLL12_HSE
62 CLK_PLL3_HSE
63 CLK_PLL4_HSE
64 CLK_RTC_LSE
65 CLK_MCO1_DISABLED
66 CLK_MCO2_DISABLED
67 >;
68
69 st,clkdiv = <
70 1 /*MPU*/
71 0 /*AXI*/
72 0 /*MCU*/
73 1 /*APB1*/
74 1 /*APB2*/
75 1 /*APB3*/
76 1 /*APB4*/
77 2 /*APB5*/
78 23 /*RTC*/
79 0 /*MCO1*/
80 0 /*MCO2*/
81 >;
82
83 st,pkcs = <
84 CLK_CKPER_HSE
85 CLK_FMC_ACLK
86 CLK_QSPI_ACLK
87 CLK_ETH_DISABLED
88 CLK_SDMMC12_PLL4P
89 CLK_DSI_DSIPLL
90 CLK_STGEN_HSE
91 CLK_USBPHY_HSE
92 CLK_SPI2S1_PLL3Q
93 CLK_SPI2S23_PLL3Q
94 CLK_SPI45_HSI
95 CLK_SPI6_HSI
96 CLK_I2C46_HSI
97 CLK_SDMMC3_PLL4P
98 CLK_USBO_USBPHY
99 CLK_ADC_CKPER
100 CLK_CEC_LSE
101 CLK_I2C12_HSI
102 CLK_I2C35_HSI
103 CLK_UART1_HSI
104 CLK_UART24_HSI
105 CLK_UART35_HSI
106 CLK_UART6_HSI
107 CLK_UART78_HSI
108 CLK_SPDIF_PLL4P
109 CLK_FDCAN_PLL4R
110 CLK_SAI1_PLL3Q
111 CLK_SAI2_PLL3Q
112 CLK_SAI3_PLL3Q
113 CLK_SAI4_PLL3Q
114 CLK_RNG1_LSI
115 CLK_RNG2_LSI
116 CLK_LPTIM1_PCLK1
117 CLK_LPTIM23_PCLK3
118 CLK_LPTIM45_LSE
119 >;
120
121 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
122 pll2: st,pll@1 {
123 compatible = "st,stm32mp1-pll";
124 reg = <1>;
125 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
126 frac = < 0x1400 >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]127 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]128 };
129
130 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
131 pll3: st,pll@2 {
132 compatible = "st,stm32mp1-pll";
133 reg = <2>;
134 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
135 frac = < 0x1a04 >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]136 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]137 };
138
139 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
140 pll4: st,pll@3 {
141 compatible = "st,stm32mp1-pll";
142 reg = <3>;
143 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]144 bootph-all;
Jagan Tekic0f218b2021-03-16 21:52:03 +0530[diff] [blame]145 };
146};