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git01.mediatek.com / filogic / uboot / 4a4ebe308448b62123703d49355feffe3f9b1590 / . / arch / arm / dts / k3-j721e-sk-u-boot.dtsi
blob: 31f979f3bb8124e6bd23ed93c845f750bbfc5e37 [file] [log] [blame]
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6#include <dt-bindings/net/ti-dp83867.h>
7
8/ {
9 chosen {
10 stdout-path = "serial2:115200n8";
11 tick-timer = &timer1;
12 };
13
14 aliases {
15 ethernet0 = &cpsw_port1;
16 spi0 = &ospi0;
17 remoteproc0 = &mcu_r5fss0_core0;
18 remoteproc1 = &mcu_r5fss0_core1;
19 remoteproc2 = &main_r5fss0_core0;
20 remoteproc3 = &main_r5fss0_core1;
21 remoteproc4 = &main_r5fss1_core0;
22 remoteproc5 = &main_r5fss1_core1;
23 remoteproc6 = &c66_0;
24 remoteproc7 = &c66_1;
25 remoteproc8 = &c71_0;
26 i2c0 = &wkup_i2c0;
27 i2c1 = &mcu_i2c0;
28 i2c2 = &main_i2c0;
29 mmc1 = &main_sdhci1; /* SD Card */
30 };
31};
32
33&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]35
Sinthu Raja490d7162023-04-03 12:03:12 -0500[diff] [blame]36 main_navss: bus@30000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]38 };
39};
40
41&cbass_mcu_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]43
44 timer1: timer@40400000 {
45 compatible = "ti,omap5430-timer";
46 reg = <0x0 0x40400000 0x0 0x80>;
47 ti,timer-alwon;
48 clock-frequency = <25000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]50 };
51
Sinthu Raja490d7162023-04-03 12:03:12 -0500[diff] [blame]52 mcu_navss: bus@28380000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]54
55 ringacc@2b800000 {
56 reg = <0x0 0x2b800000 0x0 0x400000>,
57 <0x0 0x2b000000 0x0 0x400000>,
58 <0x0 0x28590000 0x0 0x100>,
59 <0x0 0x2a500000 0x0 0x40000>,
60 <0x0 0x28440000 0x0 0x40000>;
61 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]63 };
64
65 dma-controller@285c0000 {
66 reg = <0x0 0x285c0000 0x0 0x100>,
67 <0x0 0x284c0000 0x0 0x4000>,
68 <0x0 0x2a800000 0x0 0x40000>,
69 <0x0 0x284a0000 0x0 0x4000>,
70 <0x0 0x2aa00000 0x0 0x40000>,
71 <0x0 0x28400000 0x0 0x2000>;
72 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
73 "tchanrt", "rflow";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]75 };
76 };
77
78 chipid@43000014 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]80 };
81};
82
83&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]85};
86
87&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]89 k3_sysreset: sysreset-controller {
90 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]92 };
93};
94
95&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]97};
98
99&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]101};
102
103&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]105};
106
107&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]109};
110
111&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]113};
114
115&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]117};
118
119&mcu_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]121};
122
123&main_sdhci0 {
124 status = "disabled";
125};
126
127&main_sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]128 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]129};
130
131&wiz3_pll1_refclk {
132 assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
133 assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
134};
135
136&main_usbss0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]137 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]138};
139
140&usbss0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]141 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]142};
143
144&usb0 {
145 dr_mode = "host";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]146 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]147};
148
149&wiz2_pll1_refclk {
150 assigned-clocks = <&wiz2_pll1_refclk>, <&wiz2_pll0_refclk>;
151 assigned-clock-parents = <&k3_clks 294 0>, <&k3_clks 294 11>;
152};
153
154&main_usbss1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]155 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]156};
157
158&usbss1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]159 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]160};
161
162&usb1 {
163 dr_mode = "host";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]164 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]165};
166
167&mcu_cpsw {
168 reg = <0x0 0x46000000 0x0 0x200000>,
169 <0x0 0x40f00200 0x0 0x2>;
170 reg-names = "cpsw_nuss", "mac_efuse";
171 /delete-property/ ranges;
172
173 cpsw-phy-sel@40f04040 {
174 compatible = "ti,am654-cpsw-phy-sel";
175 reg= <0x0 0x40f04040 0x0 0x4>;
176 reg-names = "gmii-sel";
177 };
178};
179
180&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]181 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]182};
183
184&wkup_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]185 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]186};
187
188&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]189 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]190};
191
192&mcu_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]193 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]194};
195
196&mcu_i2c1 {
197 status = "disabled";
198};
199
200&main_i2c0 {
201 status = "disabled";
202};
203
204&main_i2c1 {
205 status = "disabled";
206};
207
208&main_i2c2 {
209 status = "disabled";
210};
211
212&main_i2c3 {
213 status = "disabled";
214};
215
216&main_i2c4 {
217 status = "disabled";
218};
219
220&main_i2c5 {
221 status = "disabled";
222};
223
224&main_i2c6 {
225 status = "disabled";
226};
227
228&mcu_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]229 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]230};
231
232&mcu_fss0_ospi0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]233 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]234};
235
236&fss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]237 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]238};
239
Sinthu Raja490d7162023-04-03 12:03:12 -0500[diff] [blame]240&hbmc {
241 status = "disabled";
242};
243
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]244&ospi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]245 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]246
247 flash@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]248 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]249
250 partition@3fc0000 {
251 label = "ospi.phypattern";
252 reg = <0x3fc0000 0x40000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]253 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]254 };
255 };
256};
257
258&serdes_ln_ctrl {
259 u-boot,mux-autoprobe;
260};
261
262&usb_serdes_mux {
263 u-boot,mux-autoprobe;
264};
265
266&pcie0_rc {
267 status = "disabled";
268};
269
270&pcie1_rc {
271 status = "disabled";
272};
273
274&pcie0_ep {
275 status = "disabled";
276};
277
278&pcie1_ep {
279 status = "disabled";
280};
281
282&dss {
283 status = "disabled";
284};