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git01.mediatek.com / filogic / uboot / 4a33795f89bfe869558345caa0cc43d52027e2a1 / . / arch / arm / dts / zynq-cse-nor.dts
blob: a5c8a0813ffb60a472547a4bc945e7556ae6c961 [file] [log] [blame]
Siva Durga Prasad Paladuguf3e0ed42018-07-16 15:57:02 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Xilinx CSE NOR board DTS
4 *
5 * Copyright (C) 2018 Xilinx, Inc.
6 */
7/dts-v1/;
Siva Durga Prasad Paladuguf3e0ed42018-07-16 15:57:02 +0530[diff] [blame]8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 model = "Zynq CSE NOR Board";
13 compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
14
15 aliases {
16 serial0 = &dcc;
17 };
18
19 memory@fffc0000 {
20 device_type = "memory";
21 reg = <0xFFFC0000 0x40000>;
22 };
23
24 chosen {
25 stdout-path = "serial0:115200n8";
26 };
27
28 dcc: dcc {
29 compatible = "arm,dcc";
30 status = "disabled";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-all;
Siva Durga Prasad Paladuguf3e0ed42018-07-16 15:57:02 +0530[diff] [blame]32 };
33
34 amba: amba {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-all;
Siva Durga Prasad Paladuguf3e0ed42018-07-16 15:57:02 +0530[diff] [blame]36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
Siva Durga Prasad Paladuguf3e0ed42018-07-16 15:57:02 +0530[diff] [blame]39 ranges;
40
Siva Durga Prasad Paladuguf3e0ed42018-07-16 15:57:02 +0530[diff] [blame]41 slcr: slcr@f8000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-all;
Siva Durga Prasad Paladuguf3e0ed42018-07-16 15:57:02 +0530[diff] [blame]43 #address-cells = <1>;
44 #size-cells = <1>;
45 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
46 reg = <0xF8000000 0x1000>;
47 ranges;
48 clkc: clkc@100 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-all;
Siva Durga Prasad Paladuguf3e0ed42018-07-16 15:57:02 +0530[diff] [blame]50 #clock-cells = <1>;
51 compatible = "xlnx,ps7-clkc";
Siva Durga Prasad Paladuguf3e0ed42018-07-16 15:57:02 +0530[diff] [blame]52 clock-output-names = "armpll", "ddrpll",
53 "iopll", "cpu_6or4x",
54 "cpu_3or2x", "cpu_2x", "cpu_1x",
55 "ddr2x", "ddr3x", "dci",
56 "lqspi", "smc", "pcap", "gem0",
57 "gem1", "fclk0", "fclk1",
58 "fclk2", "fclk3", "can0",
59 "can1", "sdio0", "sdio1",
60 "uart0", "uart1", "spi0",
61 "spi1", "dma", "usb0_aper",
62 "usb1_aper", "gem0_aper",
63 "gem1_aper", "sdio0_aper",
64 "sdio1_aper", "spi0_aper",
65 "spi1_aper", "can0_aper",
66 "can1_aper", "i2c0_aper",
67 "i2c1_aper", "uart0_aper",
68 "uart1_aper", "gpio_aper",
69 "lqspi_aper", "smc_aper",
70 "swdt", "dbg_trc", "dbg_apb";
71 reg = <0x100 0x100>;
72 };
73 };
Michal Simekecd0ce52020-02-25 15:29:40 +0100[diff] [blame]74
75 /*
76 * This is partially hack because it is normally subnode of smcc
77 * but for mini U-Boot there is no reason to enable SMCC driver
78 * which does almost nothing in NOR flash configuration that's
79 * why place cfi-flash directly here.
80 */
81 flash@e2000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-all;
Michal Simekecd0ce52020-02-25 15:29:40 +0100[diff] [blame]83 compatible = "cfi-flash";
84 reg = <0xe2000000 0x2000000>;
85 #address-cells = <1>;
86 #size-cells = <1>;
87 };
Michal Simek34140ec2022-11-29 13:23:20 +0100[diff] [blame]88
89 scutimer: timer@f8f00600 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-all;
Michal Simek34140ec2022-11-29 13:23:20 +0100[diff] [blame]91 compatible = "arm,cortex-a9-twd-timer";
92 reg = <0xf8f00600 0x20>;
93 clock-frequency = <333333333>;
94 };
Siva Durga Prasad Paladuguf3e0ed42018-07-16 15:57:02 +0530[diff] [blame]95 };
Siva Durga Prasad Paladuguf3e0ed42018-07-16 15:57:02 +0530[diff] [blame]96};
97
98&dcc {
99 status = "okay";
100};