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Patrick Delaunayc5c90692019-11-06 16:16:32 +01001// SPDX-License-Identifier: GPL-2.0+ OR X11
Michael Kurzbccef712017-01-22 16:04:23 +01002/*
Patrice Chotard24dffa52019-02-19 16:49:05 +01003 * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
Michael Kurzbccef712017-01-22 16:04:23 +01004 *
Michael Kurzbccef712017-01-22 16:04:23 +01005 */
6
7/dts-v1/;
8#include "stm32f746.dtsi"
Patrice Chotard24dffa52019-02-19 16:49:05 +01009#include "stm32f746-pinctrl.dtsi"
10#include <dt-bindings/input/input.h>
Patrice Chotardda8f8ef2018-08-06 09:38:18 +020011#include <dt-bindings/gpio/gpio.h>
Michael Kurzbccef712017-01-22 16:04:23 +010012
13/ {
14 model = "STMicroelectronics STM32F746-DISCO board";
15 compatible = "st,stm32f746-disco", "st,stm32f746";
16
17 chosen {
Patrice Chotard24dffa52019-02-19 16:49:05 +010018 bootargs = "root=/dev/ram";
Michael Kurzbccef712017-01-22 16:04:23 +010019 stdout-path = "serial0:115200n8";
20 };
21
Patrice Chotard62f56162020-11-06 08:11:58 +010022 memory@c0000000 {
Patrick Delaunayc5c90692019-11-06 16:16:32 +010023 device_type = "memory";
Michael Kurzbccef712017-01-22 16:04:23 +010024 reg = <0xC0000000 0x800000>;
25 };
26
27 aliases {
Vikas Manochada913d32017-02-12 10:25:47 -080028 serial0 = &usart1;
Michael Kurzbccef712017-01-22 16:04:23 +010029 };
Vikas Manocha9c7573e2017-04-10 15:03:00 -070030
Patrice Chotard24dffa52019-02-19 16:49:05 +010031 usbotg_hs_phy: usb-phy {
32 #phy-cells = <0>;
33 compatible = "usb-nop-xceiv";
34 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
35 clock-names = "main_clk";
36 };
37
38 /* This turns on vbus for otg fs for host mode (dwc2) */
39 vcc5v_otg_fs: vcc5v-otg-fs-regulator {
40 compatible = "regulator-fixed";
41 gpio = <&gpiod 5 0>;
42 regulator-name = "vcc5_host1";
43 regulator-always-on;
44 };
45
46 mmc_vcard: mmc_vcard {
47 compatible = "regulator-fixed";
48 regulator-name = "mmc_vcard";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 };
Michael Kurzbccef712017-01-22 16:04:23 +010052};
53
Vikas Manochada913d32017-02-12 10:25:47 -080054&clk_hse {
55 clock-frequency = <25000000>;
56};
57
Patrice Chotard24dffa52019-02-19 16:49:05 +010058&i2c1 {
59 pinctrl-0 = <&i2c1_pins_b>;
Vikas Manocha6ad568c2017-02-12 10:25:51 -080060 pinctrl-names = "default";
Patrice Chotard24dffa52019-02-19 16:49:05 +010061 i2c-scl-rising-time-ns = <185>;
62 i2c-scl-falling-time-ns = <20>;
Vikas Manocha6ad568c2017-02-12 10:25:51 -080063 status = "okay";
64};
65
Patrice Chotard24dffa52019-02-19 16:49:05 +010066&sdio1 {
Patrice Chotard0d24b0d2017-12-12 10:14:59 +010067 status = "okay";
Patrice Chotard24dffa52019-02-19 16:49:05 +010068 vmmc-supply = <&mmc_vcard>;
Patrice Chotardda8f8ef2018-08-06 09:38:18 +020069 cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
Patrice Chotard0d24b0d2017-12-12 10:14:59 +010070 pinctrl-names = "default", "opendrain";
Patrice Chotard24dffa52019-02-19 16:49:05 +010071 pinctrl-0 = <&sdio_pins_a>;
72 pinctrl-1 = <&sdio_pins_od_a>;
Patrice Chotard0d24b0d2017-12-12 10:14:59 +010073 bus-width = <4>;
Patrice Chotard24dffa52019-02-19 16:49:05 +010074};
75
Patrice Chotard83975322022-09-23 13:20:33 +020076&timers5 {
77 /* Override timer5 to act as clockevent */
78 compatible = "st,stm32-timer";
79 interrupts = <50>;
80 status = "okay";
81 /delete-property/#address-cells;
82 /delete-property/#size-cells;
83 /delete-property/clock-names;
84 /delete-node/pwm;
85 /delete-node/timer@4;
86};
87
Patrice Chotard24dffa52019-02-19 16:49:05 +010088&usart1 {
89 pinctrl-0 = <&usart1_pins_b>;
90 pinctrl-names = "default";
91 status = "okay";
92};
93
94&usbotg_fs {
95 dr_mode = "host";
96 pinctrl-0 = <&usbotg_fs_pins_a>;
97 pinctrl-names = "default";
98 status = "okay";
99};
100
101&usbotg_hs {
102 dr_mode = "host";
103 phys = <&usbotg_hs_phy>;
104 phy-names = "usb2-phy";
105 pinctrl-0 = <&usbotg_hs_pins_b>;
106 pinctrl-names = "default";
107 status = "okay";
Patrice Chotard0d24b0d2017-12-12 10:14:59 +0100108};