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git01.mediatek.com / filogic / uboot / 4a33795f89bfe869558345caa0cc43d52027e2a1 / . / arch / arm / dts / rk3399-rockpro64.dts
blob: 4b42717800f777278802941f743c681c5c4c8465 [file] [log] [blame]
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
Jagan Teki5cc21182020-04-28 15:30:17 +0530[diff] [blame]5 * Copyright (c) 2019 Katsuhiro Suzuki <katsuhiro@katsuster.net>
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]6 */
7
8/dts-v1/;
Jagan Teki5cc21182020-04-28 15:30:17 +0530[diff] [blame]9#include "rk3399-rockpro64.dtsi"
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]10
11/ {
Jagan Teki5cc21182020-04-28 15:30:17 +0530[diff] [blame]12 model = "Pine64 RockPro64 v2.1";
13 compatible = "pine64,rockpro64-v2.1", "pine64,rockpro64", "rockchip,rk3399";
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]14};
15
16&i2c1 {
Jagan Teki5cc21182020-04-28 15:30:17 +0530[diff] [blame]17 es8316: codec@11 {
18 compatible = "everest,es8316";
19 reg = <0x11>;
20 clocks = <&cru SCLK_I2S_8CH_OUT>;
21 clock-names = "mclk";
22 #sound-dai-cells = <0>;
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]23
Jagan Teki5cc21182020-04-28 15:30:17 +0530[diff] [blame]24 port {
25 es8316_p0_0: endpoint {
26 remote-endpoint = <&i2s1_p0_0>;
27 };
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]28 };
29 };
30};