Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 1 | /* |
Igor Grinberg | e83d229 | 2013-04-22 01:06:53 +0000 | [diff] [blame] | 2 | * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il> |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 3 | * |
Igor Grinberg | bebedbf | 2011-04-18 17:48:31 -0400 | [diff] [blame] | 4 | * Authors: Mike Rapoport <mike@compulab.co.il> |
| 5 | * Igor Grinberg <grinberg@compulab.co.il> |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 6 | * |
| 7 | * Derived from omap3evm and Beagle Board by |
| 8 | * Manikandan Pillai <mani.pillai@ti.com> |
| 9 | * Richard Woodruff <r-woodruff2@ti.com> |
| 10 | * Syed Mohammed Khasim <x0khasim@ti.com> |
| 11 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 12 | * SPDX-License-Identifier: GPL-2.0+ |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <common.h> |
Igor Grinberg | d2367bc | 2011-04-18 17:54:33 -0400 | [diff] [blame] | 16 | #include <status_led.h> |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 17 | #include <netdev.h> |
| 18 | #include <net.h> |
| 19 | #include <i2c.h> |
Nikita Kiryanov | 9f957be | 2012-12-02 13:59:19 +0200 | [diff] [blame] | 20 | #include <usb.h> |
Nikita Kiryanov | 4459e76 | 2012-12-03 02:19:45 +0000 | [diff] [blame] | 21 | #include <mmc.h> |
Nikita Kiryanov | 7f9ceea | 2015-01-14 10:42:54 +0200 | [diff] [blame] | 22 | #include <splash.h> |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 23 | #include <twl4030.h> |
Nikita Kiryanov | b47cb9d | 2012-01-12 03:26:30 +0000 | [diff] [blame] | 24 | #include <linux/compiler.h> |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 25 | |
| 26 | #include <asm/io.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 27 | #include <linux/errno.h> |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 28 | #include <asm/arch/mem.h> |
| 29 | #include <asm/arch/mux.h> |
| 30 | #include <asm/arch/mmc_host_def.h> |
| 31 | #include <asm/arch/sys_proto.h> |
| 32 | #include <asm/mach-types.h> |
Nikita Kiryanov | 9f957be | 2012-12-02 13:59:19 +0200 | [diff] [blame] | 33 | #include <asm/ehci-omap.h> |
| 34 | #include <asm/gpio.h> |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 35 | |
Igor Grinberg | 3c5dc28 | 2014-11-03 11:32:18 +0200 | [diff] [blame] | 36 | #include "../common/common.h" |
Igor Grinberg | 3394be8 | 2013-09-16 21:49:58 +0300 | [diff] [blame] | 37 | #include "../common/eeprom.h" |
Nikita Kiryanov | f1ef869 | 2012-01-12 03:28:09 +0000 | [diff] [blame] | 38 | |
Igor Grinberg | 8bd1b19 | 2011-04-18 17:43:26 -0400 | [diff] [blame] | 39 | DECLARE_GLOBAL_DATA_PTR; |
| 40 | |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 41 | const omap3_sysinfo sysinfo = { |
| 42 | DDR_DISCRETE, |
Igor Grinberg | 05a96a4 | 2011-04-18 17:55:21 -0400 | [diff] [blame] | 43 | "CM-T3x board", |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 44 | "NAND", |
| 45 | }; |
| 46 | |
Stefan Roese | 8ef10bd | 2013-12-04 13:54:18 +0100 | [diff] [blame] | 47 | #ifdef CONFIG_SPL_BUILD |
| 48 | /* |
| 49 | * Routine: get_board_mem_timings |
| 50 | * Description: If we use SPL then there is no x-loader nor config header |
| 51 | * so we have to setup the DDR timings ourself on both banks. |
| 52 | */ |
| 53 | void get_board_mem_timings(struct board_sdrc_timings *timings) |
| 54 | { |
| 55 | timings->mr = MICRON_V_MR_165; |
| 56 | timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */ |
| 57 | timings->ctrla = MICRON_V_ACTIMA_165; |
| 58 | timings->ctrlb = MICRON_V_ACTIMB_165; |
| 59 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; |
| 60 | } |
| 61 | #endif |
| 62 | |
Nikita Kiryanov | c2a07e3 | 2015-01-14 10:42:51 +0200 | [diff] [blame] | 63 | struct splash_location splash_locations[] = { |
| 64 | { |
| 65 | .name = "nand", |
| 66 | .storage = SPLASH_STORAGE_NAND, |
Nikita Kiryanov | 7428271 | 2015-10-29 11:54:41 +0200 | [diff] [blame] | 67 | .flags = SPLASH_STORAGE_RAW, |
Nikita Kiryanov | c2a07e3 | 2015-01-14 10:42:51 +0200 | [diff] [blame] | 68 | .offset = 0x100000, |
| 69 | }, |
| 70 | }; |
Igor Grinberg | 86ec16b | 2014-11-03 11:32:20 +0200 | [diff] [blame] | 71 | |
Robert Winkler | 2abfe36 | 2013-06-17 11:31:31 -0700 | [diff] [blame] | 72 | int splash_screen_prepare(void) |
Nikita Kiryanov | c4a295a | 2012-12-22 21:03:48 +0000 | [diff] [blame] | 73 | { |
Nikita Kiryanov | 7f9ceea | 2015-01-14 10:42:54 +0200 | [diff] [blame] | 74 | return splash_source_load(splash_locations, |
| 75 | ARRAY_SIZE(splash_locations)); |
Nikita Kiryanov | c4a295a | 2012-12-22 21:03:48 +0000 | [diff] [blame] | 76 | } |
Nikita Kiryanov | c4a295a | 2012-12-22 21:03:48 +0000 | [diff] [blame] | 77 | |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 78 | /* |
| 79 | * Routine: board_init |
Igor Grinberg | 7e741ff | 2012-06-13 19:41:40 +0000 | [diff] [blame] | 80 | * Description: hardware init. |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 81 | */ |
| 82 | int board_init(void) |
| 83 | { |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 84 | gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
| 85 | |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 86 | /* board id for Linux */ |
Igor Grinberg | 05a96a4 | 2011-04-18 17:55:21 -0400 | [diff] [blame] | 87 | if (get_cpu_family() == CPU_OMAP34XX) |
| 88 | gd->bd->bi_arch_number = MACH_TYPE_CM_T35; |
| 89 | else |
| 90 | gd->bd->bi_arch_number = MACH_TYPE_CM_T3730; |
| 91 | |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 92 | /* boot param addr */ |
| 93 | gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); |
| 94 | |
Uri Mashiach | 4892d39 | 2017-01-19 10:51:45 +0200 | [diff] [blame] | 95 | #if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) |
| 96 | status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON); |
Igor Grinberg | d2367bc | 2011-04-18 17:54:33 -0400 | [diff] [blame] | 97 | #endif |
| 98 | |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 99 | return 0; |
| 100 | } |
| 101 | |
Nikita Kiryanov | cc935c6 | 2012-05-24 04:01:24 +0000 | [diff] [blame] | 102 | /* |
| 103 | * Routine: get_board_rev |
| 104 | * Description: read system revision |
| 105 | */ |
| 106 | u32 get_board_rev(void) |
| 107 | { |
Nikita Kiryanov | 7fa6835 | 2015-09-06 11:48:35 +0300 | [diff] [blame] | 108 | return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS); |
Nikita Kiryanov | cc935c6 | 2012-05-24 04:01:24 +0000 | [diff] [blame] | 109 | }; |
| 110 | |
Nikita Kiryanov | cc935c6 | 2012-05-24 04:01:24 +0000 | [diff] [blame] | 111 | int misc_init_r(void) |
| 112 | { |
Igor Grinberg | 3c5dc28 | 2014-11-03 11:32:18 +0200 | [diff] [blame] | 113 | cl_print_pcb_info(); |
Paul Kocialkowski | 6bc318e | 2015-08-27 19:37:13 +0200 | [diff] [blame] | 114 | omap_die_id_display(); |
Nikita Kiryanov | cc935c6 | 2012-05-24 04:01:24 +0000 | [diff] [blame] | 115 | |
| 116 | return 0; |
| 117 | } |
| 118 | |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 119 | /* |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 120 | * Routine: set_muxconf_regs |
| 121 | * Description: Setting up the configuration Mux registers specific to the |
| 122 | * hardware. Many pins need to be moved from protect to primary |
| 123 | * mode. |
| 124 | */ |
Igor Grinberg | 05a96a4 | 2011-04-18 17:55:21 -0400 | [diff] [blame] | 125 | static void cm_t3x_set_common_muxconf(void) |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 126 | { |
| 127 | /* SDRC */ |
| 128 | MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ |
| 129 | MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ |
| 130 | MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ |
| 131 | MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ |
| 132 | MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ |
| 133 | MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ |
| 134 | MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ |
| 135 | MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ |
| 136 | MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ |
| 137 | MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ |
| 138 | MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ |
| 139 | MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ |
| 140 | MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ |
| 141 | MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ |
| 142 | MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ |
| 143 | MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ |
| 144 | MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ |
| 145 | MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ |
| 146 | MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ |
| 147 | MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ |
| 148 | MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ |
| 149 | MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ |
| 150 | MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ |
| 151 | MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ |
| 152 | MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ |
| 153 | MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ |
| 154 | MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ |
| 155 | MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ |
| 156 | MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ |
| 157 | MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ |
| 158 | MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ |
| 159 | MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ |
| 160 | MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ |
| 161 | MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ |
| 162 | MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ |
| 163 | MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ |
| 164 | MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ |
| 165 | MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ |
| 166 | MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ |
| 167 | |
| 168 | /* GPMC */ |
| 169 | MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ |
| 170 | MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ |
| 171 | MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ |
| 172 | MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ |
| 173 | MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ |
| 174 | MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ |
| 175 | MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ |
| 176 | MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ |
| 177 | MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ |
| 178 | MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ |
| 179 | MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ |
| 180 | MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ |
| 181 | MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ |
| 182 | MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ |
| 183 | MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ |
| 184 | MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ |
| 185 | MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ |
| 186 | MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ |
| 187 | MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ |
| 188 | MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ |
| 189 | MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ |
| 190 | MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ |
| 191 | MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ |
| 192 | MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ |
| 193 | MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ |
| 194 | MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ |
| 195 | MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ |
| 196 | |
| 197 | /* SB-T35 Ethernet */ |
| 198 | MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ |
| 199 | |
Nikita Kiryanov | 2247eb4 | 2013-01-30 21:39:58 +0000 | [diff] [blame] | 200 | /* DVI enable */ |
| 201 | MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ |
| 202 | |
Nikita Kiryanov | 25da152 | 2013-10-16 17:23:29 +0300 | [diff] [blame] | 203 | /* DataImage backlight */ |
| 204 | MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ |
| 205 | |
Igor Grinberg | 05a96a4 | 2011-04-18 17:55:21 -0400 | [diff] [blame] | 206 | /* CM-T3x Ethernet */ |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 207 | MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ |
| 208 | MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ |
| 209 | MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ |
| 210 | MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ |
| 211 | MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/ |
| 212 | MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ |
| 213 | MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/ |
| 214 | MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/ |
| 215 | MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ |
| 216 | |
| 217 | /* DSS */ |
| 218 | MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/ |
| 219 | MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ |
| 220 | MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ |
| 221 | MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 222 | MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ |
| 223 | MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ |
| 224 | MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ |
| 225 | MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/ |
| 226 | MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/ |
| 227 | MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/ |
| 228 | MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/ |
| 229 | MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/ |
| 230 | MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/ |
| 231 | MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ |
| 232 | MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ |
| 233 | MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 234 | |
| 235 | /* serial interface */ |
| 236 | MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ |
| 237 | MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/ |
| 238 | |
| 239 | /* mUSB */ |
| 240 | MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ |
| 241 | MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ |
| 242 | MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ |
| 243 | MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ |
| 244 | MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ |
| 245 | MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ |
| 246 | MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ |
| 247 | MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ |
| 248 | MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ |
| 249 | MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ |
| 250 | MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ |
| 251 | MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ |
| 252 | |
Nikita Kiryanov | 9f957be | 2012-12-02 13:59:19 +0200 | [diff] [blame] | 253 | /* USB EHCI */ |
| 254 | MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ |
| 255 | MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ |
| 256 | MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ |
| 257 | MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ |
| 258 | MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ |
| 259 | MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ |
| 260 | MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ |
| 261 | MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ |
| 262 | MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ |
| 263 | MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ |
| 264 | MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ |
| 265 | MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ |
| 266 | |
| 267 | MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ |
| 268 | MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ |
| 269 | MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ |
| 270 | MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ |
| 271 | MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ |
| 272 | MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ |
| 273 | MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ |
| 274 | MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ |
| 275 | MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ |
| 276 | MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ |
| 277 | MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ |
| 278 | MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ |
| 279 | |
| 280 | /* SB_T35_USB_HUB_RESET_GPIO */ |
| 281 | MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ |
| 282 | |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 283 | /* I2C1 */ |
| 284 | MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ |
| 285 | MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ |
Nikita Kiryanov | da4da30 | 2012-04-02 02:29:31 +0000 | [diff] [blame] | 286 | /* I2C2 */ |
| 287 | MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ |
| 288 | MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ |
| 289 | /* I2C3 */ |
| 290 | MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ |
| 291 | MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 292 | |
| 293 | /* control and debug */ |
| 294 | MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ |
| 295 | MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ |
| 296 | MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ |
| 297 | MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ |
| 298 | MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ |
Igor Grinberg | d2367bc | 2011-04-18 17:54:33 -0400 | [diff] [blame] | 299 | MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ |
Igor Grinberg | 165808d | 2014-10-21 18:25:30 +0300 | [diff] [blame] | 300 | MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/ |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 301 | MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ |
| 302 | MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ |
| 303 | MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ |
Igor Grinberg | a704ce0 | 2011-04-18 17:50:07 -0400 | [diff] [blame] | 304 | |
| 305 | /* MMC1 */ |
| 306 | MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ |
| 307 | MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ |
| 308 | MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ |
| 309 | MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ |
| 310 | MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ |
| 311 | MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ |
Nikita Kiryanov | 25da152 | 2013-10-16 17:23:29 +0300 | [diff] [blame] | 312 | |
| 313 | /* SPI */ |
| 314 | MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ |
| 315 | MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ |
| 316 | MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ |
| 317 | MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ |
| 318 | |
| 319 | /* display controls */ |
| 320 | MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ |
Igor Grinberg | 05a96a4 | 2011-04-18 17:55:21 -0400 | [diff] [blame] | 321 | } |
| 322 | |
| 323 | static void cm_t35_set_muxconf(void) |
| 324 | { |
| 325 | /* DSS */ |
| 326 | MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ |
| 327 | MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ |
| 328 | MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ |
| 329 | MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ |
| 330 | MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ |
| 331 | MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ |
| 332 | |
| 333 | MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ |
| 334 | MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ |
| 335 | MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ |
| 336 | MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ |
| 337 | MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ |
| 338 | MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ |
| 339 | |
| 340 | /* MMC1 */ |
Igor Grinberg | a704ce0 | 2011-04-18 17:50:07 -0400 | [diff] [blame] | 341 | MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ |
| 342 | MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ |
| 343 | MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ |
| 344 | MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 345 | } |
| 346 | |
Igor Grinberg | 05a96a4 | 2011-04-18 17:55:21 -0400 | [diff] [blame] | 347 | static void cm_t3730_set_muxconf(void) |
| 348 | { |
| 349 | /* DSS */ |
| 350 | MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/ |
| 351 | MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/ |
| 352 | MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/ |
| 353 | MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/ |
| 354 | MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/ |
| 355 | MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/ |
| 356 | |
| 357 | MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/ |
| 358 | MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/ |
| 359 | MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/ |
| 360 | MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/ |
| 361 | MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/ |
| 362 | MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/ |
| 363 | } |
| 364 | |
| 365 | void set_muxconf_regs(void) |
| 366 | { |
| 367 | cm_t3x_set_common_muxconf(); |
| 368 | |
| 369 | if (get_cpu_family() == CPU_OMAP34XX) |
| 370 | cm_t35_set_muxconf(); |
| 371 | else |
| 372 | cm_t3730_set_muxconf(); |
| 373 | } |
| 374 | |
Masahiro Yamada | 0a78017 | 2017-05-09 20:31:39 +0900 | [diff] [blame] | 375 | #if defined(CONFIG_MMC) |
Igor Grinberg | de25e2d | 2014-10-21 16:39:46 +0300 | [diff] [blame] | 376 | #define SB_T35_WP_GPIO 59 |
| 377 | |
Nikita Kiryanov | 4459e76 | 2012-12-03 02:19:45 +0000 | [diff] [blame] | 378 | int board_mmc_getcd(struct mmc *mmc) |
| 379 | { |
| 380 | u8 val; |
| 381 | |
Nishanth Menon | 5d9d6f7 | 2013-03-26 05:20:50 +0000 | [diff] [blame] | 382 | if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val)) |
Nikita Kiryanov | 4459e76 | 2012-12-03 02:19:45 +0000 | [diff] [blame] | 383 | return -1; |
| 384 | |
| 385 | return !(val & 1); |
| 386 | } |
| 387 | |
Tom Rini | d0974a8 | 2011-09-03 21:49:24 -0400 | [diff] [blame] | 388 | int board_mmc_init(bd_t *bis) |
| 389 | { |
Igor Grinberg | de25e2d | 2014-10-21 16:39:46 +0300 | [diff] [blame] | 390 | return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO); |
Tom Rini | d0974a8 | 2011-09-03 21:49:24 -0400 | [diff] [blame] | 391 | } |
| 392 | #endif |
| 393 | |
Masahiro Yamada | 0a78017 | 2017-05-09 20:31:39 +0900 | [diff] [blame] | 394 | #if defined(CONFIG_MMC) |
Paul Kocialkowski | 6955989 | 2014-11-08 20:55:47 +0100 | [diff] [blame] | 395 | void board_mmc_power_init(void) |
| 396 | { |
| 397 | twl4030_power_mmc_init(0); |
| 398 | } |
| 399 | #endif |
| 400 | |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 401 | #ifdef CONFIG_SYS_I2C_OMAP34XX |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 402 | /* |
| 403 | * Routine: reset_net_chip |
| 404 | * Description: reset the Ethernet controller via TPS65930 GPIO |
| 405 | */ |
Igor Grinberg | fd6cd35 | 2014-11-03 11:32:21 +0200 | [diff] [blame] | 406 | static int cm_t3x_reset_net_chip(int gpio) |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 407 | { |
| 408 | /* Set GPIO1 of TPS65930 as output */ |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 409 | twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, |
| 410 | 0x02); |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 411 | /* Send a pulse on the GPIO pin */ |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 412 | twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, |
| 413 | 0x02); |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 414 | udelay(1); |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 415 | twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09, |
| 416 | 0x02); |
Igor Grinberg | e4d26a2 | 2012-04-02 20:12:58 +0000 | [diff] [blame] | 417 | mdelay(40); |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 418 | twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, |
| 419 | 0x02); |
Igor Grinberg | e4d26a2 | 2012-04-02 20:12:58 +0000 | [diff] [blame] | 420 | mdelay(1); |
Igor Grinberg | fd6cd35 | 2014-11-03 11:32:21 +0200 | [diff] [blame] | 421 | return 0; |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 422 | } |
| 423 | #else |
Igor Grinberg | fd6cd35 | 2014-11-03 11:32:21 +0200 | [diff] [blame] | 424 | static inline int cm_t3x_reset_net_chip(int gpio) { return 0; } |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 425 | #endif |
| 426 | |
Nikita Kiryanov | b7792f0 | 2012-01-02 04:01:31 +0000 | [diff] [blame] | 427 | #ifdef CONFIG_SMC911X |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 428 | /* |
| 429 | * Routine: handle_mac_address |
| 430 | * Description: prepare MAC address for on-board Ethernet. |
| 431 | */ |
| 432 | static int handle_mac_address(void) |
| 433 | { |
| 434 | unsigned char enetaddr[6]; |
| 435 | int rc; |
| 436 | |
| 437 | rc = eth_getenv_enetaddr("ethaddr", enetaddr); |
| 438 | if (rc) |
| 439 | return 0; |
| 440 | |
Nikita Kiryanov | b2c5547 | 2015-01-14 10:42:43 +0200 | [diff] [blame] | 441 | rc = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 442 | if (rc) |
| 443 | return rc; |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 444 | |
Joe Hershberger | 8ecdbed | 2015-04-08 01:41:04 -0500 | [diff] [blame] | 445 | if (!is_valid_ethaddr(enetaddr)) |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 446 | return -1; |
| 447 | |
| 448 | return eth_setenv_enetaddr("ethaddr", enetaddr); |
| 449 | } |
| 450 | |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 451 | /* |
| 452 | * Routine: board_eth_init |
| 453 | * Description: initialize module and base-board Ethernet chips |
| 454 | */ |
| 455 | int board_eth_init(bd_t *bis) |
| 456 | { |
| 457 | int rc = 0, rc1 = 0; |
| 458 | |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 459 | rc1 = handle_mac_address(); |
| 460 | if (rc1) |
Igor Grinberg | 7e741ff | 2012-06-13 19:41:40 +0000 | [diff] [blame] | 461 | printf("No MAC address found! "); |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 462 | |
Igor Grinberg | fd6cd35 | 2014-11-03 11:32:21 +0200 | [diff] [blame] | 463 | rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE, |
| 464 | cm_t3x_reset_net_chip, -EINVAL); |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 465 | if (rc1 > 0) |
| 466 | rc++; |
| 467 | |
Igor Grinberg | fd6cd35 | 2014-11-03 11:32:21 +0200 | [diff] [blame] | 468 | rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL); |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 469 | if (rc1 > 0) |
| 470 | rc++; |
Mike Rapoport | 8abe730 | 2010-12-18 17:43:19 -0500 | [diff] [blame] | 471 | |
| 472 | return rc; |
| 473 | } |
Nikita Kiryanov | b7792f0 | 2012-01-02 04:01:31 +0000 | [diff] [blame] | 474 | #endif |
Nikita Kiryanov | b47cb9d | 2012-01-12 03:26:30 +0000 | [diff] [blame] | 475 | |
Nikita Kiryanov | 9f957be | 2012-12-02 13:59:19 +0200 | [diff] [blame] | 476 | #ifdef CONFIG_USB_EHCI_OMAP |
| 477 | struct omap_usbhs_board_data usbhs_bdata = { |
| 478 | .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, |
| 479 | .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, |
| 480 | .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, |
| 481 | }; |
| 482 | |
| 483 | #define SB_T35_USB_HUB_RESET_GPIO 167 |
Troy Kisky | 7d6bbb9 | 2013-10-10 15:27:57 -0700 | [diff] [blame] | 484 | int ehci_hcd_init(int index, enum usb_init_type init, |
Igor Grinberg | 9c687fd | 2014-11-03 11:32:19 +0200 | [diff] [blame] | 485 | struct ehci_hccr **hccr, struct ehci_hcor **hcor) |
Nikita Kiryanov | 9f957be | 2012-12-02 13:59:19 +0200 | [diff] [blame] | 486 | { |
| 487 | u8 val; |
| 488 | int offset; |
| 489 | |
Igor Grinberg | 9c687fd | 2014-11-03 11:32:19 +0200 | [diff] [blame] | 490 | cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); |
Nikita Kiryanov | 9f957be | 2012-12-02 13:59:19 +0200 | [diff] [blame] | 491 | |
| 492 | offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; |
Nishanth Menon | 5d9d6f7 | 2013-03-26 05:20:50 +0000 | [diff] [blame] | 493 | twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); |
Nikita Kiryanov | 9f957be | 2012-12-02 13:59:19 +0200 | [diff] [blame] | 494 | /* Set GPIO6 and GPIO7 of TPS65930 as output */ |
| 495 | val |= 0xC0; |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 496 | twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val); |
Nikita Kiryanov | 9f957be | 2012-12-02 13:59:19 +0200 | [diff] [blame] | 497 | offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; |
| 498 | /* Take both PHYs out of reset */ |
Nishanth Menon | d26a106 | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 499 | twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0); |
Nikita Kiryanov | 9f957be | 2012-12-02 13:59:19 +0200 | [diff] [blame] | 500 | udelay(1); |
| 501 | |
Mateusz Zalega | d862f89 | 2013-10-04 19:22:26 +0200 | [diff] [blame] | 502 | return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); |
Nikita Kiryanov | 9f957be | 2012-12-02 13:59:19 +0200 | [diff] [blame] | 503 | } |
| 504 | |
| 505 | int ehci_hcd_stop(void) |
| 506 | { |
Igor Grinberg | 9c687fd | 2014-11-03 11:32:19 +0200 | [diff] [blame] | 507 | cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); |
Nikita Kiryanov | 9f957be | 2012-12-02 13:59:19 +0200 | [diff] [blame] | 508 | return omap_ehci_hcd_stop(); |
| 509 | } |
Nikita Kiryanov | 9f957be | 2012-12-02 13:59:19 +0200 | [diff] [blame] | 510 | #endif /* CONFIG_USB_EHCI_OMAP */ |