Vignesh R | 3f5fb8b | 2019-02-05 11:29:25 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * |
| 4 | * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. |
| 5 | * Copyright (C) 2016 Jagan Teki <jagan@openedev.com> |
| 6 | * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <spi.h> |
| 11 | #include <spi_flash.h> |
| 12 | |
| 13 | #include "sf_internal.h" |
| 14 | |
| 15 | /* Exclude chip names for SPL to save space */ |
| 16 | #if !CONFIG_IS_ENABLED(SPI_FLASH_TINY) |
| 17 | #define INFO_NAME(_name) .name = _name, |
| 18 | #else |
| 19 | #define INFO_NAME(_name) |
| 20 | #endif |
| 21 | |
| 22 | /* Used when the "_ext_id" is two bytes at most */ |
| 23 | #define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
| 24 | INFO_NAME(_name) \ |
| 25 | .id = { \ |
| 26 | ((_jedec_id) >> 16) & 0xff, \ |
| 27 | ((_jedec_id) >> 8) & 0xff, \ |
| 28 | (_jedec_id) & 0xff, \ |
| 29 | ((_ext_id) >> 8) & 0xff, \ |
| 30 | (_ext_id) & 0xff, \ |
| 31 | }, \ |
| 32 | .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ |
| 33 | .sector_size = (_sector_size), \ |
| 34 | .n_sectors = (_n_sectors), \ |
| 35 | .page_size = 256, \ |
| 36 | .flags = (_flags), |
| 37 | |
| 38 | #define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
| 39 | INFO_NAME(_name) \ |
| 40 | .id = { \ |
| 41 | ((_jedec_id) >> 16) & 0xff, \ |
| 42 | ((_jedec_id) >> 8) & 0xff, \ |
| 43 | (_jedec_id) & 0xff, \ |
| 44 | ((_ext_id) >> 16) & 0xff, \ |
| 45 | ((_ext_id) >> 8) & 0xff, \ |
| 46 | (_ext_id) & 0xff, \ |
| 47 | }, \ |
| 48 | .id_len = 6, \ |
| 49 | .sector_size = (_sector_size), \ |
| 50 | .n_sectors = (_n_sectors), \ |
| 51 | .page_size = 256, \ |
| 52 | .flags = (_flags), |
| 53 | |
| 54 | /* NOTE: double check command sets and memory organization when you add |
| 55 | * more nor chips. This current list focusses on newer chips, which |
| 56 | * have been converging on command sets which including JEDEC ID. |
| 57 | * |
| 58 | * All newly added entries should describe *hardware* and should use SECT_4K |
| 59 | * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage |
| 60 | * scenarios excluding small sectors there is config option that can be |
Vignesh Raghavendra | a5cf613 | 2019-09-26 19:04:27 +0530 | [diff] [blame] | 61 | * disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS. |
Vignesh R | 3f5fb8b | 2019-02-05 11:29:25 +0530 | [diff] [blame] | 62 | * For historical (and compatibility) reasons (before we got above config) some |
| 63 | * old entries may be missing 4K flag. |
| 64 | */ |
| 65 | const struct flash_info spi_nor_ids[] = { |
| 66 | #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ |
| 67 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
| 68 | { INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, |
| 69 | { INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, |
| 70 | |
| 71 | { INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) }, |
| 72 | { INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) }, |
| 73 | { INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) }, |
| 74 | { INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, |
| 75 | { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) }, |
| 76 | { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, |
| 77 | { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, |
| 78 | { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, |
| 79 | #endif |
| 80 | #ifdef CONFIG_SPI_FLASH_EON /* EON */ |
| 81 | /* EON -- en25xxx */ |
| 82 | { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, |
| 83 | { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, |
| 84 | { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, |
| 85 | { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, |
| 86 | #endif |
| 87 | #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ |
| 88 | /* GigaDevice */ |
| 89 | { |
| 90 | INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32, |
| 91 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 92 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 93 | }, |
| 94 | { |
| 95 | INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64, |
| 96 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 97 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 98 | }, |
| 99 | { |
| 100 | INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64, |
| 101 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 102 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 103 | }, |
| 104 | { |
| 105 | INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128, |
| 106 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 107 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 108 | }, |
Neil Armstrong | 3f83d7d | 2019-04-12 11:50:10 +0200 | [diff] [blame] | 109 | { |
| 110 | INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, |
| 111 | SECT_4K | SPI_NOR_DUAL_READ | |
| 112 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 113 | }, |
Vignesh R | 3f5fb8b | 2019-02-05 11:29:25 +0530 | [diff] [blame] | 114 | #endif |
| 115 | #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ |
| 116 | /* ISSI */ |
| 117 | { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8, |
| 118 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 119 | { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) }, |
| 120 | { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) }, |
| 121 | { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, |
| 122 | SECT_4K | SPI_NOR_DUAL_READ) }, |
| 123 | { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512, |
| 124 | SECT_4K | SPI_NOR_DUAL_READ) }, |
| 125 | { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, |
| 126 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 127 | { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128, |
| 128 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 129 | { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256, |
| 130 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
Jagan Teki | ae04794 | 2019-09-29 13:12:37 +0530 | [diff] [blame] | 131 | { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512, |
| 132 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
Vignesh R | 3f5fb8b | 2019-02-05 11:29:25 +0530 | [diff] [blame] | 133 | #endif |
| 134 | #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ |
| 135 | /* Macronix */ |
| 136 | { INFO("mx25l2005a", 0xc22012, 0, 64 * 1024, 4, SECT_4K) }, |
| 137 | { INFO("mx25l4005a", 0xc22013, 0, 64 * 1024, 8, SECT_4K) }, |
| 138 | { INFO("mx25l8005", 0xc22014, 0, 64 * 1024, 16, 0) }, |
| 139 | { INFO("mx25l1606e", 0xc22015, 0, 64 * 1024, 32, SECT_4K) }, |
| 140 | { INFO("mx25l3205d", 0xc22016, 0, 64 * 1024, 64, SECT_4K) }, |
| 141 | { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) }, |
| 142 | { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) }, |
| 143 | { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) }, |
| 144 | { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, |
| 145 | { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) }, |
| 146 | { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, |
| 147 | { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 148 | { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, |
| 149 | { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, |
| 150 | { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, |
| 151 | { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, |
Marek Vasut | 942a420 | 2019-03-07 23:27:46 +0100 | [diff] [blame] | 152 | { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, |
Vignesh R | 3f5fb8b | 2019-02-05 11:29:25 +0530 | [diff] [blame] | 153 | { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 154 | { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, |
| 155 | #endif |
| 156 | |
| 157 | #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ |
| 158 | /* Micron */ |
| 159 | { INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, |
| 160 | { INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
| 161 | { INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
| 162 | { INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
| 163 | { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
| 164 | { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, |
| 165 | { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, |
Vignesh Raghavendra | f53bd81 | 2019-10-11 13:28:19 +0530 | [diff] [blame^] | 166 | { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, |
Vignesh Raghavendra | 84acf73 | 2019-10-11 13:28:18 +0530 | [diff] [blame] | 167 | { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
Vignesh Raghavendra | f53bd81 | 2019-10-11 13:28:19 +0530 | [diff] [blame^] | 168 | { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, |
Vignesh Raghavendra | 84acf73 | 2019-10-11 13:28:18 +0530 | [diff] [blame] | 169 | { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, |
Ashish Kumar | 8a201a0 | 2019-07-17 11:45:00 +0530 | [diff] [blame] | 170 | { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, |
| 171 | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, |
Vignesh Raghavendra | 84acf73 | 2019-10-11 13:28:18 +0530 | [diff] [blame] | 172 | { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, |
Vignesh Raghavendra | f53bd81 | 2019-10-11 13:28:19 +0530 | [diff] [blame^] | 173 | { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, |
Vignesh Raghavendra | 84acf73 | 2019-10-11 13:28:18 +0530 | [diff] [blame] | 174 | { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, |
Vignesh R | 3f5fb8b | 2019-02-05 11:29:25 +0530 | [diff] [blame] | 175 | { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, |
| 176 | { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, |
| 177 | { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, |
Ashish Kumar | 820de7e | 2019-07-18 16:43:15 +0530 | [diff] [blame] | 178 | { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_4B_OPCODES) }, |
| 179 | { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_4B_OPCODES) }, |
Vignesh R | 3f5fb8b | 2019-02-05 11:29:25 +0530 | [diff] [blame] | 180 | #endif |
| 181 | #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ |
| 182 | /* Spansion/Cypress -- single (large) sector size only, at least |
| 183 | * for the chips listed here (without boot sectors). |
| 184 | */ |
| 185 | { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 186 | { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 187 | { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) }, |
| 188 | { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, |
| 189 | { INFO6("s25fl512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, |
| 190 | { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, |
| 191 | { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, |
| 192 | { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, |
| 193 | { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, |
| 194 | { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, |
| 195 | { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, |
| 196 | { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, |
| 197 | { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, |
| 198 | { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) }, |
| 199 | { INFO("s25sl016a", 0x010214, 0, 64 * 1024, 32, 0) }, |
| 200 | { INFO("s25sl032a", 0x010215, 0, 64 * 1024, 64, 0) }, |
| 201 | { INFO("s25sl064a", 0x010216, 0, 64 * 1024, 128, 0) }, |
| 202 | { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 203 | { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) }, |
| 204 | { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, |
Heiko Schocher | 50aad82 | 2019-02-08 11:03:39 +0100 | [diff] [blame] | 205 | { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, |
Vignesh R | 3f5fb8b | 2019-02-05 11:29:25 +0530 | [diff] [blame] | 206 | { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, |
| 207 | #endif |
| 208 | #ifdef CONFIG_SPI_FLASH_SST /* SST */ |
| 209 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ |
| 210 | { INFO("sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, |
| 211 | { INFO("sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, |
| 212 | { INFO("sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, |
| 213 | { INFO("sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, |
| 214 | { INFO("sst25vf064c", 0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, |
| 215 | { INFO("sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, |
| 216 | { INFO("sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, |
| 217 | { INFO("sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, |
| 218 | { INFO("sst25wf020a", 0x621612, 0, 64 * 1024, 4, SECT_4K) }, |
| 219 | { INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) }, |
| 220 | { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, |
| 221 | { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, |
Eugeniy Paltsev | 9c9d8d5 | 2019-09-09 22:33:15 +0300 | [diff] [blame] | 222 | { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 223 | { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, |
| 224 | { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, |
| 225 | { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, |
Vignesh R | 3f5fb8b | 2019-02-05 11:29:25 +0530 | [diff] [blame] | 226 | #endif |
| 227 | #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ |
| 228 | /* ST Microelectronics -- newer production may have feature updates */ |
| 229 | { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) }, |
| 230 | { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) }, |
| 231 | { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) }, |
| 232 | { INFO("m25p80", 0x202014, 0, 64 * 1024, 16, 0) }, |
| 233 | { INFO("m25p16", 0x202015, 0, 64 * 1024, 32, 0) }, |
| 234 | { INFO("m25p32", 0x202016, 0, 64 * 1024, 64, 0) }, |
| 235 | { INFO("m25p64", 0x202017, 0, 64 * 1024, 128, 0) }, |
| 236 | { INFO("m25p128", 0x202018, 0, 256 * 1024, 64, 0) }, |
| 237 | { INFO("m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K) }, |
| 238 | { INFO("m25px16", 0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 239 | { INFO("m25px64", 0x207117, 0, 64 * 1024, 128, 0) }, |
| 240 | #endif |
| 241 | #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ |
| 242 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ |
| 243 | { INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) }, |
| 244 | { INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) }, |
| 245 | { INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) }, |
| 246 | { INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) }, |
| 247 | { INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) }, |
| 248 | { INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) }, |
| 249 | { |
| 250 | INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, |
| 251 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 252 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 253 | }, |
| 254 | { INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) }, |
| 255 | { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) }, |
| 256 | { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, |
| 257 | { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, |
| 258 | { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 259 | { |
| 260 | INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, |
| 261 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 262 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 263 | }, |
| 264 | { |
| 265 | INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64, |
| 266 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 267 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 268 | }, |
| 269 | { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) }, |
| 270 | { |
| 271 | INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128, |
| 272 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 273 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 274 | }, |
| 275 | { |
| 276 | INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128, |
| 277 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 278 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 279 | }, |
| 280 | { |
| 281 | INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256, |
| 282 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 283 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 284 | }, |
| 285 | { |
| 286 | INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256, |
| 287 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 288 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 289 | }, |
| 290 | { |
| 291 | INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512, |
| 292 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 293 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 294 | }, |
| 295 | { |
| 296 | INFO("w25q256jw", 0xef7019, 0, 64 * 1024, 512, |
| 297 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
| 298 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) |
| 299 | }, |
| 300 | { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, |
| 301 | { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 302 | { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 303 | { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 304 | { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 305 | { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 306 | #endif |
| 307 | #ifdef CONFIG_SPI_FLASH_XMC |
| 308 | /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ |
| 309 | { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 310 | { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 311 | #endif |
| 312 | { }, |
| 313 | }; |