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git01.mediatek.com / filogic / uboot / 488f0e7d5672ade8d5c6869712c376e7c8001086 / . / board / LaCie / netspace_v2 / netspace_v2.c
blob: 453c0dd46780d2ab36c20f8582aaabe96a07f95a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]2/*
3 * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
4 *
5 * Based on Kirkwood support:
6 * (C) Copyright 2009
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]9 */
10
11#include <common.h>
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]12#include <command.h>
Alex Kiernan9c215492018-04-01 09:22:38 +0000[diff] [blame]13#include <environment.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -0600[diff] [blame]14#include <asm/mach-types.h>
Anatolij Gustschin5cf80f12011-10-29 11:31:19 +0000[diff] [blame]15#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]16#include <asm/arch/soc.h>
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]17#include <asm/arch/mpp.h>
18#include <asm/arch/gpio.h>
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]19
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]20#include "netspace_v2.h"
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]21#include "../common/common.h"
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]22
23DECLARE_GLOBAL_DATA_PTR;
24
25int board_early_init_f(void)
26{
27 /* Gpio configuration */
Stefan Roesec50ab392014-10-22 12:13:11 +0200[diff] [blame]28 mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
29 NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]30
31 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]32 static const u32 kwmpp_config[] = {
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]33 MPP0_SPI_SCn,
34 MPP1_SPI_MOSI,
35 MPP2_SPI_SCK,
36 MPP3_SPI_MISO,
37 MPP4_NF_IO6,
38 MPP5_NF_IO7,
39 MPP6_SYSRST_OUTn,
40 MPP7_GPO, /* Fan speed (bit 1) */
41 MPP8_TW_SDA,
42 MPP9_TW_SCK,
43 MPP10_UART0_TXD,
44 MPP11_UART0_RXD,
45 MPP12_GPO, /* Red led */
46 MPP14_GPIO, /* USB fuse */
47 MPP16_GPIO, /* SATA 0 power */
48 MPP17_GPIO, /* SATA 1 power */
49 MPP18_NF_IO0,
50 MPP19_NF_IO1,
51 MPP20_SATA1_ACTn,
52 MPP21_SATA0_ACTn,
53 MPP22_GPIO, /* Fan speed (bit 0) */
54 MPP23_GPIO, /* Fan power */
55 MPP24_GPIO, /* USB mode select */
56 MPP25_GPIO, /* Fan rotation fail */
57 MPP26_GPIO, /* USB vbus-in detection */
58 MPP28_GPIO, /* USB enable vbus-out */
59 MPP29_GPIO, /* Blue led (slow register) */
60 MPP30_GPIO, /* Blue led (command register) */
61 MPP31_GPIO, /* Board power off */
62 MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */
63 MPP33_GPIO, /* Fan speed (bit 2) */
64 0
65 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]66 kirkwood_mpp_conf(kwmpp_config, NULL);
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]67
68 return 0;
69}
70
71int board_init(void)
72{
73 /* Machine number */
74 gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
75
76 /* Boot parameters address */
Stefan Roese0b741752014-10-22 12:13:13 +0200[diff] [blame]77 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]78
79 return 0;
80}
81
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]82#if defined(CONFIG_MISC_INIT_R)
Simon Guinot6e238912011-11-08 11:31:14 +0000[diff] [blame]83int misc_init_r(void)
84{
85#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
Simon Glass64b723f2017-08-03 12:22:12 -0600[diff] [blame]86 if (!env_get("ethaddr")) {
Simon Guinot6e238912011-11-08 11:31:14 +0000[diff] [blame]87 uchar mac[6];
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]88 if (lacie_read_mac_address(mac) == 0)
Simon Glass8551d552017-08-03 12:22:11 -0600[diff] [blame]89 eth_env_set_enetaddr("ethaddr", mac);
Simon Guinot6e238912011-11-08 11:31:14 +0000[diff] [blame]90 }
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]91#endif
Simon Guinot6e238912011-11-08 11:31:14 +0000[diff] [blame]92 return 0;
93}
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]94#endif
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]95
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]96#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]97/* Configure and initialize PHY */
98void reset_phy(void)
99{
Simon Guinot13c5ae62012-09-06 10:51:42 +0000[diff] [blame]100#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
101 mv_phy_88e1318_init("egiga0", 0);
102#else
Simon Guinot0473b682012-06-05 13:16:00 +0000[diff] [blame]103 mv_phy_88e1116_init("egiga0", 8);
Simon Guinot13c5ae62012-09-06 10:51:42 +0000[diff] [blame]104#endif
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]105}
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]106#endif
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]107
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]108#if defined(CONFIG_KIRKWOOD_GPIO)
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]109/* Return GPIO button status */
110static int
111do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
112{
113 return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
114}
115
116U_BOOT_CMD(button, 1, 1, do_read_button,
117 "Return GPIO button status 0=off 1=on", "");
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]118#endif