Bin Meng | c85a5be | 2018-10-15 02:21:23 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> |
| 4 | * |
| 5 | * VirtIO PCI bus transport driver |
| 6 | * Ported from Linux drivers/virtio/virtio_pci*.c |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <dm.h> |
| 11 | #include <virtio_types.h> |
| 12 | #include <virtio.h> |
| 13 | #include <virtio_ring.h> |
| 14 | #include <dm/device.h> |
| 15 | #include <linux/compat.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 16 | #include <linux/err.h> |
Bin Meng | c85a5be | 2018-10-15 02:21:23 -0700 | [diff] [blame] | 17 | #include <linux/io.h> |
| 18 | #include "virtio_pci.h" |
| 19 | |
| 20 | #define VIRTIO_PCI_DRV_NAME "virtio-pci.m" |
| 21 | |
| 22 | /* PCI device ID in the range 0x1040 to 0x107f */ |
| 23 | #define VIRTIO_PCI_VENDOR_ID 0x1af4 |
| 24 | #define VIRTIO_PCI_DEVICE_ID00 0x1040 |
| 25 | #define VIRTIO_PCI_DEVICE_ID01 0x1041 |
| 26 | #define VIRTIO_PCI_DEVICE_ID02 0x1042 |
| 27 | #define VIRTIO_PCI_DEVICE_ID03 0x1043 |
| 28 | #define VIRTIO_PCI_DEVICE_ID04 0x1044 |
| 29 | #define VIRTIO_PCI_DEVICE_ID05 0x1045 |
| 30 | #define VIRTIO_PCI_DEVICE_ID06 0x1046 |
| 31 | #define VIRTIO_PCI_DEVICE_ID07 0x1047 |
| 32 | #define VIRTIO_PCI_DEVICE_ID08 0x1048 |
| 33 | #define VIRTIO_PCI_DEVICE_ID09 0x1049 |
| 34 | #define VIRTIO_PCI_DEVICE_ID0A 0x104a |
| 35 | #define VIRTIO_PCI_DEVICE_ID0B 0x104b |
| 36 | #define VIRTIO_PCI_DEVICE_ID0C 0x104c |
| 37 | #define VIRTIO_PCI_DEVICE_ID0D 0x104d |
| 38 | #define VIRTIO_PCI_DEVICE_ID0E 0x104e |
| 39 | #define VIRTIO_PCI_DEVICE_ID0F 0x104f |
| 40 | #define VIRTIO_PCI_DEVICE_ID10 0x1050 |
| 41 | #define VIRTIO_PCI_DEVICE_ID11 0x1051 |
| 42 | #define VIRTIO_PCI_DEVICE_ID12 0x1052 |
| 43 | #define VIRTIO_PCI_DEVICE_ID13 0x1053 |
| 44 | #define VIRTIO_PCI_DEVICE_ID14 0x1054 |
| 45 | #define VIRTIO_PCI_DEVICE_ID15 0x1055 |
| 46 | #define VIRTIO_PCI_DEVICE_ID16 0x1056 |
| 47 | #define VIRTIO_PCI_DEVICE_ID17 0x1057 |
| 48 | #define VIRTIO_PCI_DEVICE_ID18 0x1058 |
| 49 | #define VIRTIO_PCI_DEVICE_ID19 0x1059 |
| 50 | #define VIRTIO_PCI_DEVICE_ID1A 0x105a |
| 51 | #define VIRTIO_PCI_DEVICE_ID1B 0x105b |
| 52 | #define VIRTIO_PCI_DEVICE_ID1C 0x105c |
| 53 | #define VIRTIO_PCI_DEVICE_ID1D 0x105d |
| 54 | #define VIRTIO_PCI_DEVICE_ID1E 0x105e |
| 55 | #define VIRTIO_PCI_DEVICE_ID1F 0x105f |
| 56 | #define VIRTIO_PCI_DEVICE_ID20 0x1060 |
| 57 | #define VIRTIO_PCI_DEVICE_ID21 0x1061 |
| 58 | #define VIRTIO_PCI_DEVICE_ID22 0x1062 |
| 59 | #define VIRTIO_PCI_DEVICE_ID23 0x1063 |
| 60 | #define VIRTIO_PCI_DEVICE_ID24 0x1064 |
| 61 | #define VIRTIO_PCI_DEVICE_ID25 0x1065 |
| 62 | #define VIRTIO_PCI_DEVICE_ID26 0x1066 |
| 63 | #define VIRTIO_PCI_DEVICE_ID27 0x1067 |
| 64 | #define VIRTIO_PCI_DEVICE_ID28 0x1068 |
| 65 | #define VIRTIO_PCI_DEVICE_ID29 0x1069 |
| 66 | #define VIRTIO_PCI_DEVICE_ID2A 0x106a |
| 67 | #define VIRTIO_PCI_DEVICE_ID2B 0x106b |
| 68 | #define VIRTIO_PCI_DEVICE_ID2C 0x106c |
| 69 | #define VIRTIO_PCI_DEVICE_ID2D 0x106d |
| 70 | #define VIRTIO_PCI_DEVICE_ID2E 0x106e |
| 71 | #define VIRTIO_PCI_DEVICE_ID2F 0x106f |
| 72 | #define VIRTIO_PCI_DEVICE_ID30 0x1070 |
| 73 | #define VIRTIO_PCI_DEVICE_ID31 0x1071 |
| 74 | #define VIRTIO_PCI_DEVICE_ID32 0x1072 |
| 75 | #define VIRTIO_PCI_DEVICE_ID33 0x1073 |
| 76 | #define VIRTIO_PCI_DEVICE_ID34 0x1074 |
| 77 | #define VIRTIO_PCI_DEVICE_ID35 0x1075 |
| 78 | #define VIRTIO_PCI_DEVICE_ID36 0x1076 |
| 79 | #define VIRTIO_PCI_DEVICE_ID37 0x1077 |
| 80 | #define VIRTIO_PCI_DEVICE_ID38 0x1078 |
| 81 | #define VIRTIO_PCI_DEVICE_ID39 0x1079 |
| 82 | #define VIRTIO_PCI_DEVICE_ID3A 0x107a |
| 83 | #define VIRTIO_PCI_DEVICE_ID3B 0x107b |
| 84 | #define VIRTIO_PCI_DEVICE_ID3C 0x107c |
| 85 | #define VIRTIO_PCI_DEVICE_ID3D 0x107d |
| 86 | #define VIRTIO_PCI_DEVICE_ID3E 0x107e |
| 87 | #define VIRTIO_PCI_DEVICE_ID3F 0x107f |
| 88 | |
| 89 | /** |
| 90 | * virtio pci transport driver private data |
| 91 | * |
| 92 | * @common: pci transport device common register block base |
| 93 | * @notify_base: pci transport device notify register block base |
| 94 | * @device: pci transport device device-specific register block base |
| 95 | * @device_len: pci transport device device-specific register block length |
| 96 | * @notify_offset_multiplier: multiply queue_notify_off by this value |
| 97 | */ |
| 98 | struct virtio_pci_priv { |
| 99 | struct virtio_pci_common_cfg __iomem *common; |
| 100 | void __iomem *notify_base; |
| 101 | void __iomem *device; |
| 102 | u32 device_len; |
| 103 | u32 notify_offset_multiplier; |
| 104 | }; |
| 105 | |
| 106 | static int virtio_pci_get_config(struct udevice *udev, unsigned int offset, |
| 107 | void *buf, unsigned int len) |
| 108 | { |
| 109 | struct virtio_pci_priv *priv = dev_get_priv(udev); |
| 110 | u8 b; |
| 111 | __le16 w; |
| 112 | __le32 l; |
| 113 | |
| 114 | WARN_ON(offset + len > priv->device_len); |
| 115 | |
| 116 | switch (len) { |
| 117 | case 1: |
| 118 | b = ioread8(priv->device + offset); |
| 119 | memcpy(buf, &b, sizeof(b)); |
| 120 | break; |
| 121 | case 2: |
| 122 | w = cpu_to_le16(ioread16(priv->device + offset)); |
| 123 | memcpy(buf, &w, sizeof(w)); |
| 124 | break; |
| 125 | case 4: |
| 126 | l = cpu_to_le32(ioread32(priv->device + offset)); |
| 127 | memcpy(buf, &l, sizeof(l)); |
| 128 | break; |
| 129 | case 8: |
| 130 | l = cpu_to_le32(ioread32(priv->device + offset)); |
| 131 | memcpy(buf, &l, sizeof(l)); |
| 132 | l = cpu_to_le32(ioread32(priv->device + offset + sizeof(l))); |
| 133 | memcpy(buf + sizeof(l), &l, sizeof(l)); |
| 134 | break; |
| 135 | default: |
| 136 | WARN_ON(true); |
| 137 | } |
| 138 | |
| 139 | return 0; |
| 140 | } |
| 141 | |
| 142 | static int virtio_pci_set_config(struct udevice *udev, unsigned int offset, |
| 143 | const void *buf, unsigned int len) |
| 144 | { |
| 145 | struct virtio_pci_priv *priv = dev_get_priv(udev); |
| 146 | u8 b; |
| 147 | __le16 w; |
| 148 | __le32 l; |
| 149 | |
| 150 | WARN_ON(offset + len > priv->device_len); |
| 151 | |
| 152 | switch (len) { |
| 153 | case 1: |
| 154 | memcpy(&b, buf, sizeof(b)); |
| 155 | iowrite8(b, priv->device + offset); |
| 156 | break; |
| 157 | case 2: |
| 158 | memcpy(&w, buf, sizeof(w)); |
| 159 | iowrite16(le16_to_cpu(w), priv->device + offset); |
| 160 | break; |
| 161 | case 4: |
| 162 | memcpy(&l, buf, sizeof(l)); |
| 163 | iowrite32(le32_to_cpu(l), priv->device + offset); |
| 164 | break; |
| 165 | case 8: |
| 166 | memcpy(&l, buf, sizeof(l)); |
| 167 | iowrite32(le32_to_cpu(l), priv->device + offset); |
| 168 | memcpy(&l, buf + sizeof(l), sizeof(l)); |
| 169 | iowrite32(le32_to_cpu(l), priv->device + offset + sizeof(l)); |
| 170 | break; |
| 171 | default: |
| 172 | WARN_ON(true); |
| 173 | } |
| 174 | |
| 175 | return 0; |
| 176 | } |
| 177 | |
| 178 | static int virtio_pci_generation(struct udevice *udev, u32 *counter) |
| 179 | { |
| 180 | struct virtio_pci_priv *priv = dev_get_priv(udev); |
| 181 | |
| 182 | *counter = ioread8(&priv->common->config_generation); |
| 183 | |
| 184 | return 0; |
| 185 | } |
| 186 | |
| 187 | static int virtio_pci_get_status(struct udevice *udev, u8 *status) |
| 188 | { |
| 189 | struct virtio_pci_priv *priv = dev_get_priv(udev); |
| 190 | |
| 191 | *status = ioread8(&priv->common->device_status); |
| 192 | |
| 193 | return 0; |
| 194 | } |
| 195 | |
| 196 | static int virtio_pci_set_status(struct udevice *udev, u8 status) |
| 197 | { |
| 198 | struct virtio_pci_priv *priv = dev_get_priv(udev); |
| 199 | |
| 200 | /* We should never be setting status to 0 */ |
| 201 | WARN_ON(status == 0); |
| 202 | |
| 203 | iowrite8(status, &priv->common->device_status); |
| 204 | |
| 205 | return 0; |
| 206 | } |
| 207 | |
| 208 | static int virtio_pci_reset(struct udevice *udev) |
| 209 | { |
| 210 | struct virtio_pci_priv *priv = dev_get_priv(udev); |
| 211 | |
| 212 | /* 0 status means a reset */ |
| 213 | iowrite8(0, &priv->common->device_status); |
| 214 | |
| 215 | /* |
| 216 | * After writing 0 to device_status, the driver MUST wait for a read |
| 217 | * of device_status to return 0 before reinitializing the device. |
| 218 | * This will flush out the status write, and flush in device writes, |
| 219 | * including MSI-X interrupts, if any. |
| 220 | */ |
| 221 | while (ioread8(&priv->common->device_status)) |
| 222 | udelay(1000); |
| 223 | |
| 224 | return 0; |
| 225 | } |
| 226 | |
| 227 | static int virtio_pci_get_features(struct udevice *udev, u64 *features) |
| 228 | { |
| 229 | struct virtio_pci_priv *priv = dev_get_priv(udev); |
| 230 | |
| 231 | iowrite32(0, &priv->common->device_feature_select); |
| 232 | *features = ioread32(&priv->common->device_feature); |
| 233 | iowrite32(1, &priv->common->device_feature_select); |
| 234 | *features |= ((u64)ioread32(&priv->common->device_feature) << 32); |
| 235 | |
| 236 | return 0; |
| 237 | } |
| 238 | |
| 239 | static int virtio_pci_set_features(struct udevice *udev) |
| 240 | { |
| 241 | struct virtio_pci_priv *priv = dev_get_priv(udev); |
| 242 | struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); |
| 243 | |
| 244 | if (!__virtio_test_bit(udev, VIRTIO_F_VERSION_1)) { |
| 245 | debug("virtio: device uses modern interface but does not have VIRTIO_F_VERSION_1\n"); |
| 246 | return -EINVAL; |
| 247 | } |
| 248 | |
| 249 | iowrite32(0, &priv->common->guest_feature_select); |
| 250 | iowrite32((u32)uc_priv->features, &priv->common->guest_feature); |
| 251 | iowrite32(1, &priv->common->guest_feature_select); |
| 252 | iowrite32(uc_priv->features >> 32, &priv->common->guest_feature); |
| 253 | |
| 254 | return 0; |
| 255 | } |
| 256 | |
| 257 | static struct virtqueue *virtio_pci_setup_vq(struct udevice *udev, |
| 258 | unsigned int index) |
| 259 | { |
| 260 | struct virtio_pci_priv *priv = dev_get_priv(udev); |
| 261 | struct virtio_pci_common_cfg __iomem *cfg = priv->common; |
| 262 | struct virtqueue *vq; |
| 263 | u16 num; |
| 264 | u64 addr; |
| 265 | int err; |
| 266 | |
| 267 | if (index >= ioread16(&cfg->num_queues)) |
| 268 | return ERR_PTR(-ENOENT); |
| 269 | |
| 270 | /* Select the queue we're interested in */ |
| 271 | iowrite16(index, &cfg->queue_select); |
| 272 | |
| 273 | /* Check if queue is either not available or already active */ |
| 274 | num = ioread16(&cfg->queue_size); |
| 275 | if (!num || ioread16(&cfg->queue_enable)) |
| 276 | return ERR_PTR(-ENOENT); |
| 277 | |
| 278 | if (num & (num - 1)) { |
| 279 | printf("(%s): bad queue size %u", udev->name, num); |
| 280 | return ERR_PTR(-EINVAL); |
| 281 | } |
| 282 | |
| 283 | /* Create the vring */ |
| 284 | vq = vring_create_virtqueue(index, num, VIRTIO_PCI_VRING_ALIGN, udev); |
| 285 | if (!vq) { |
| 286 | err = -ENOMEM; |
| 287 | goto error_available; |
| 288 | } |
| 289 | |
| 290 | /* Activate the queue */ |
| 291 | iowrite16(virtqueue_get_vring_size(vq), &cfg->queue_size); |
| 292 | |
| 293 | addr = virtqueue_get_desc_addr(vq); |
| 294 | iowrite32((u32)addr, &cfg->queue_desc_lo); |
| 295 | iowrite32(addr >> 32, &cfg->queue_desc_hi); |
| 296 | |
| 297 | addr = virtqueue_get_avail_addr(vq); |
| 298 | iowrite32((u32)addr, &cfg->queue_avail_lo); |
| 299 | iowrite32(addr >> 32, &cfg->queue_avail_hi); |
| 300 | |
| 301 | addr = virtqueue_get_used_addr(vq); |
| 302 | iowrite32((u32)addr, &cfg->queue_used_lo); |
| 303 | iowrite32(addr >> 32, &cfg->queue_used_hi); |
| 304 | |
| 305 | iowrite16(1, &cfg->queue_enable); |
| 306 | |
| 307 | return vq; |
| 308 | |
| 309 | error_available: |
| 310 | return ERR_PTR(err); |
| 311 | } |
| 312 | |
| 313 | static void virtio_pci_del_vq(struct virtqueue *vq) |
| 314 | { |
| 315 | struct virtio_pci_priv *priv = dev_get_priv(vq->vdev); |
| 316 | unsigned int index = vq->index; |
| 317 | |
| 318 | iowrite16(index, &priv->common->queue_select); |
| 319 | |
| 320 | /* Select and deactivate the queue */ |
| 321 | iowrite16(0, &priv->common->queue_enable); |
| 322 | |
| 323 | vring_del_virtqueue(vq); |
| 324 | } |
| 325 | |
| 326 | static int virtio_pci_del_vqs(struct udevice *udev) |
| 327 | { |
| 328 | struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); |
| 329 | struct virtqueue *vq, *n; |
| 330 | |
| 331 | list_for_each_entry_safe(vq, n, &uc_priv->vqs, list) |
| 332 | virtio_pci_del_vq(vq); |
| 333 | |
| 334 | return 0; |
| 335 | } |
| 336 | |
| 337 | static int virtio_pci_find_vqs(struct udevice *udev, unsigned int nvqs, |
| 338 | struct virtqueue *vqs[]) |
| 339 | { |
| 340 | int i; |
| 341 | |
| 342 | for (i = 0; i < nvqs; ++i) { |
| 343 | vqs[i] = virtio_pci_setup_vq(udev, i); |
| 344 | if (IS_ERR(vqs[i])) { |
| 345 | virtio_pci_del_vqs(udev); |
| 346 | return PTR_ERR(vqs[i]); |
| 347 | } |
| 348 | } |
| 349 | |
| 350 | return 0; |
| 351 | } |
| 352 | |
| 353 | static int virtio_pci_notify(struct udevice *udev, struct virtqueue *vq) |
| 354 | { |
| 355 | struct virtio_pci_priv *priv = dev_get_priv(udev); |
| 356 | u16 off; |
| 357 | |
| 358 | /* Select the queue we're interested in */ |
| 359 | iowrite16(vq->index, &priv->common->queue_select); |
| 360 | |
| 361 | /* get offset of notification word for this vq */ |
| 362 | off = ioread16(&priv->common->queue_notify_off); |
| 363 | |
| 364 | /* |
| 365 | * We write the queue's selector into the notification register |
| 366 | * to signal the other end |
| 367 | */ |
| 368 | iowrite16(vq->index, |
| 369 | priv->notify_base + off * priv->notify_offset_multiplier); |
| 370 | |
| 371 | return 0; |
| 372 | } |
| 373 | |
| 374 | /** |
| 375 | * virtio_pci_find_capability - walk capabilities to find device info |
| 376 | * |
| 377 | * @udev: the transport device |
| 378 | * @cfg_type: the VIRTIO_PCI_CAP_* value we seek |
| 379 | * |
| 380 | * @return offset of the configuration structure |
| 381 | */ |
| 382 | static int virtio_pci_find_capability(struct udevice *udev, u8 cfg_type) |
| 383 | { |
| 384 | int pos; |
| 385 | int offset; |
| 386 | u8 type, bar; |
| 387 | |
| 388 | for (pos = dm_pci_find_capability(udev, PCI_CAP_ID_VNDR); |
| 389 | pos > 0; |
| 390 | pos = dm_pci_find_next_capability(udev, pos, PCI_CAP_ID_VNDR)) { |
| 391 | offset = pos + offsetof(struct virtio_pci_cap, cfg_type); |
| 392 | dm_pci_read_config8(udev, offset, &type); |
| 393 | offset = pos + offsetof(struct virtio_pci_cap, bar); |
| 394 | dm_pci_read_config8(udev, offset, &bar); |
| 395 | |
| 396 | /* Ignore structures with reserved BAR values */ |
| 397 | if (bar > 0x5) |
| 398 | continue; |
| 399 | |
| 400 | if (type == cfg_type) |
| 401 | return pos; |
| 402 | } |
| 403 | |
| 404 | return 0; |
| 405 | } |
| 406 | |
| 407 | /** |
| 408 | * virtio_pci_map_capability - map base address of the capability |
| 409 | * |
| 410 | * @udev: the transport device |
| 411 | * @off: offset of the configuration structure |
| 412 | * |
| 413 | * @return base address of the capability |
| 414 | */ |
| 415 | static void __iomem *virtio_pci_map_capability(struct udevice *udev, int off) |
| 416 | { |
| 417 | u8 bar; |
| 418 | u32 offset; |
| 419 | ulong base; |
| 420 | void __iomem *p; |
| 421 | |
| 422 | if (!off) |
| 423 | return NULL; |
| 424 | |
| 425 | offset = off + offsetof(struct virtio_pci_cap, bar); |
| 426 | dm_pci_read_config8(udev, offset, &bar); |
| 427 | offset = off + offsetof(struct virtio_pci_cap, offset); |
| 428 | dm_pci_read_config32(udev, offset, &offset); |
| 429 | |
| 430 | /* |
| 431 | * TODO: adding 64-bit BAR support |
| 432 | * |
| 433 | * Per spec, the BAR is permitted to be either 32-bit or 64-bit. |
| 434 | * For simplicity, only read the BAR address as 32-bit. |
| 435 | */ |
| 436 | base = dm_pci_read_bar32(udev, bar); |
| 437 | p = (void __iomem *)base + offset; |
| 438 | |
| 439 | return p; |
| 440 | } |
| 441 | |
| 442 | static int virtio_pci_bind(struct udevice *udev) |
| 443 | { |
| 444 | static int num_devs; |
| 445 | char name[20]; |
| 446 | |
| 447 | /* Create a unique device name */ |
| 448 | sprintf(name, "%s#%u", VIRTIO_PCI_DRV_NAME, num_devs++); |
| 449 | device_set_name(udev, name); |
| 450 | |
| 451 | return 0; |
| 452 | } |
| 453 | |
| 454 | static int virtio_pci_probe(struct udevice *udev) |
| 455 | { |
| 456 | struct pci_child_platdata *pplat = dev_get_parent_platdata(udev); |
| 457 | struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); |
| 458 | struct virtio_pci_priv *priv = dev_get_priv(udev); |
| 459 | u16 subvendor; |
| 460 | u8 revision; |
| 461 | int common, notify, device; |
| 462 | int offset; |
| 463 | |
| 464 | /* We only own devices >= 0x1040 and <= 0x107f: leave the rest. */ |
| 465 | if (pplat->device < 0x1040 || pplat->device > 0x107f) |
| 466 | return -ENODEV; |
| 467 | |
| 468 | /* Transitional devices must not have a PCI revision ID of 0 */ |
| 469 | dm_pci_read_config8(udev, PCI_REVISION_ID, &revision); |
| 470 | |
| 471 | /* Modern devices: simply use PCI device id, but start from 0x1040. */ |
| 472 | uc_priv->device = pplat->device - 0x1040; |
| 473 | dm_pci_read_config16(udev, PCI_SUBSYSTEM_VENDOR_ID, &subvendor); |
| 474 | uc_priv->vendor = subvendor; |
| 475 | |
| 476 | /* Check for a common config: if not, use legacy mode (bar 0) */ |
| 477 | common = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_COMMON_CFG); |
| 478 | if (!common) { |
| 479 | printf("(%s): leaving for legacy driver\n", udev->name); |
| 480 | return -ENODEV; |
| 481 | } |
| 482 | |
| 483 | /* If common is there, notify should be too */ |
| 484 | notify = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_NOTIFY_CFG); |
| 485 | if (!notify) { |
| 486 | printf("(%s): missing capabilities %i/%i\n", udev->name, |
| 487 | common, notify); |
| 488 | return -EINVAL; |
| 489 | } |
| 490 | |
| 491 | /* |
| 492 | * Device capability is only mandatory for devices that have |
| 493 | * device-specific configuration. |
| 494 | */ |
| 495 | device = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_DEVICE_CFG); |
| 496 | if (device) { |
| 497 | offset = notify + offsetof(struct virtio_pci_cap, length); |
| 498 | dm_pci_read_config32(udev, offset, &priv->device_len); |
| 499 | } |
| 500 | |
| 501 | /* Map configuration structures */ |
| 502 | priv->common = virtio_pci_map_capability(udev, common); |
| 503 | priv->notify_base = virtio_pci_map_capability(udev, notify); |
| 504 | priv->device = virtio_pci_map_capability(udev, device); |
| 505 | debug("(%p): common @ %p, notify base @ %p, device @ %p\n", |
| 506 | udev, priv->common, priv->notify_base, priv->device); |
| 507 | |
| 508 | /* Read notify_off_multiplier from config space */ |
| 509 | offset = notify + offsetof(struct virtio_pci_notify_cap, |
| 510 | notify_off_multiplier); |
| 511 | dm_pci_read_config32(udev, offset, &priv->notify_offset_multiplier); |
| 512 | |
| 513 | debug("(%s): device (%d) vendor (%08x) version (%d)\n", udev->name, |
| 514 | uc_priv->device, uc_priv->vendor, revision); |
| 515 | |
| 516 | return 0; |
| 517 | } |
| 518 | |
| 519 | static const struct dm_virtio_ops virtio_pci_ops = { |
| 520 | .get_config = virtio_pci_get_config, |
| 521 | .set_config = virtio_pci_set_config, |
| 522 | .generation = virtio_pci_generation, |
| 523 | .get_status = virtio_pci_get_status, |
| 524 | .set_status = virtio_pci_set_status, |
| 525 | .reset = virtio_pci_reset, |
| 526 | .get_features = virtio_pci_get_features, |
| 527 | .set_features = virtio_pci_set_features, |
| 528 | .find_vqs = virtio_pci_find_vqs, |
| 529 | .del_vqs = virtio_pci_del_vqs, |
| 530 | .notify = virtio_pci_notify, |
| 531 | }; |
| 532 | |
| 533 | U_BOOT_DRIVER(virtio_pci_modern) = { |
| 534 | .name = VIRTIO_PCI_DRV_NAME, |
| 535 | .id = UCLASS_VIRTIO, |
| 536 | .ops = &virtio_pci_ops, |
| 537 | .bind = virtio_pci_bind, |
| 538 | .probe = virtio_pci_probe, |
| 539 | .priv_auto_alloc_size = sizeof(struct virtio_pci_priv), |
| 540 | }; |
| 541 | |
| 542 | static struct pci_device_id virtio_pci_supported[] = { |
| 543 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID00) }, |
| 544 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID01) }, |
| 545 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID02) }, |
| 546 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID03) }, |
| 547 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID04) }, |
| 548 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID05) }, |
| 549 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID06) }, |
| 550 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID07) }, |
| 551 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID08) }, |
| 552 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID09) }, |
| 553 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0A) }, |
| 554 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0B) }, |
| 555 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0C) }, |
| 556 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0D) }, |
| 557 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0E) }, |
| 558 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0F) }, |
| 559 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID10) }, |
| 560 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID11) }, |
| 561 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID12) }, |
| 562 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID13) }, |
| 563 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID14) }, |
| 564 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID15) }, |
| 565 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID16) }, |
| 566 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID17) }, |
| 567 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID18) }, |
| 568 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID19) }, |
| 569 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1A) }, |
| 570 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1B) }, |
| 571 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1C) }, |
| 572 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1D) }, |
| 573 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1E) }, |
| 574 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1F) }, |
| 575 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID20) }, |
| 576 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID21) }, |
| 577 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID22) }, |
| 578 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID23) }, |
| 579 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID24) }, |
| 580 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID25) }, |
| 581 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID26) }, |
| 582 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID27) }, |
| 583 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID28) }, |
| 584 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID29) }, |
| 585 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2A) }, |
| 586 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2B) }, |
| 587 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2C) }, |
| 588 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2D) }, |
| 589 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2E) }, |
| 590 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2F) }, |
| 591 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID30) }, |
| 592 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID31) }, |
| 593 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID32) }, |
| 594 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID33) }, |
| 595 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID34) }, |
| 596 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID35) }, |
| 597 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID36) }, |
| 598 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID37) }, |
| 599 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID38) }, |
| 600 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID39) }, |
| 601 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3A) }, |
| 602 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3B) }, |
| 603 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3C) }, |
| 604 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3D) }, |
| 605 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3E) }, |
| 606 | { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3F) }, |
| 607 | {}, |
| 608 | }; |
| 609 | |
| 610 | U_BOOT_PCI_DEVICE(virtio_pci_modern, virtio_pci_supported); |