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git01.mediatek.com / filogic / uboot / 4808fbc9f79deab7934b3eb2518a8a39870e11d5 / . / arch / arm / include / asm / arch-rockchip / grf_rv1108.h
blob: 92bbe34af68c3029d2e2c46224830323e6ebde5f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Andy Yan96c3da92017-06-01 18:00:10 +0800[diff] [blame]2/*
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
Andy Yan96c3da92017-06-01 18:00:10 +0800[diff] [blame]4 */
5#ifndef _ASM_ARCH_GRF_RV1108_H
6#define _ASM_ARCH_GRF_RV1108_H
7
Andy Yan96c3da92017-06-01 18:00:10 +0800[diff] [blame]8struct rv1108_grf {
9 u32 reserved[4];
10 u32 gpio1a_iomux;
11 u32 gpio1b_iomux;
12 u32 gpio1c_iomux;
13 u32 gpio1d_iomux;
14 u32 gpio2a_iomux;
15 u32 gpio2b_iomux;
16 u32 gpio2c_iomux;
17 u32 gpio2d_iomux;
18 u32 gpio3a_iomux;
19 u32 gpio3b_iomux;
20 u32 gpio3c_iomux;
21 u32 gpio3d_iomux;
22 u32 reserved1[52];
23 u32 gpio1a_pull;
24 u32 gpio1b_pull;
25 u32 gpio1c_pull;
26 u32 gpio1d_pull;
27 u32 gpio2a_pull;
28 u32 gpio2b_pull;
29 u32 gpio2c_pull;
30 u32 gpio2d_pull;
31 u32 gpio3a_pull;
32 u32 gpio3b_pull;
33 u32 gpio3c_pull;
34 u32 gpio3d_pull;
35 u32 reserved2[52];
36 u32 gpio1a_drv;
37 u32 gpio1b_drv;
38 u32 gpio1c_drv;
39 u32 gpio1d_drv;
40 u32 gpio2a_drv;
41 u32 gpio2b_drv;
42 u32 gpio2c_drv;
43 u32 gpio2d_drv;
44 u32 gpio3a_drv;
45 u32 gpio3b_drv;
46 u32 gpio3c_drv;
47 u32 gpio3d_drv;
48 u32 reserved3[50];
49 u32 gpio1l_sr;
50 u32 gpio1h_sr;
51 u32 gpio2l_sr;
52 u32 gpio2h_sr;
53 u32 gpio3l_sr;
54 u32 gpio3h_sr;
55 u32 reserved4[26];
56 u32 gpio1l_smt;
57 u32 gpio1h_smt;
58 u32 gpio2l_smt;
59 u32 gpio2h_smt;
60 u32 gpio3l_smt;
61 u32 gpio3h_smt;
62 u32 reserved5[24];
63 u32 soc_con0;
64 u32 soc_con1;
65 u32 soc_con2;
66 u32 soc_con3;
67 u32 soc_con4;
68 u32 soc_con5;
69 u32 soc_con6;
70 u32 soc_con7;
71 u32 soc_con8;
72 u32 soc_con9;
73 u32 soc_con10;
74 u32 soc_con11;
75 u32 reserved6[20];
76 u32 soc_status0;
77 u32 soc_status1;
78 u32 reserved7[30];
79 u32 cpu_con0;
80 u32 cpu_con1;
81 u32 reserved8[30];
82 u32 os_reg0;
83 u32 os_reg1;
84 u32 os_reg2;
85 u32 os_reg3;
86 u32 reserved9[29];
87 u32 ddr_status;
88 u32 reserved10[30];
89 u32 sig_det_con;
90 u32 reserved11[3];
91 u32 sig_det_status;
92 u32 reserved12[3];
93 u32 sig_det_clr;
94 u32 reserved13[23];
95 u32 host_con0;
96 u32 host_con1;
97 u32 reserved14[2];
98 u32 dma_con0;
99 u32 dma_con1;
David Wua6ce7302018-01-13 13:53:56 +0800[diff] [blame]100 u32 reserved15[59];
Andy Yan96c3da92017-06-01 18:00:10 +0800[diff] [blame]101 u32 uoc_status;
David Wua6ce7302018-01-13 13:53:56 +0800[diff] [blame]102 u32 reserved16[2];
Andy Yan96c3da92017-06-01 18:00:10 +0800[diff] [blame]103 u32 host_status;
David Wua6ce7302018-01-13 13:53:56 +0800[diff] [blame]104 u32 reserved17[59];
Andy Yan96c3da92017-06-01 18:00:10 +0800[diff] [blame]105 u32 gmac_con0;
David Wua6ce7302018-01-13 13:53:56 +0800[diff] [blame]106 u32 reserved18[191];
Andy Yan96c3da92017-06-01 18:00:10 +0800[diff] [blame]107 u32 chip_id;
108};
David Wua6ce7302018-01-13 13:53:56 +0800[diff] [blame]109
110check_member(rv1108_grf, chip_id, 0x0c00);
Andy Yan96c3da92017-06-01 18:00:10 +0800[diff] [blame]111#endif