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git01.mediatek.com / filogic / uboot / 4778a378d96286f77518f7d4d5072acaf496facf / . / include / common_timing_params.h
blob: 96704cd2fce230931d17a829cb6dd0894797a538 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]2/*
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]4 */
5
6#ifndef COMMON_TIMING_PARAMS_H
7#define COMMON_TIMING_PARAMS_H
8
9typedef struct {
10 /* parameters to constrict */
11
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]12 unsigned int tckmin_x_ps;
13 unsigned int tckmax_ps;
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]14 unsigned int trcd_ps;
15 unsigned int trp_ps;
16 unsigned int tras_ps;
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]17#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
18 unsigned int taamin_ps;
19#endif
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]20
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]21#ifdef CONFIG_SYS_FSL_DDR4
22 unsigned int trfc1_ps;
23 unsigned int trfc2_ps;
24 unsigned int trfc4_ps;
25 unsigned int trrds_ps;
26 unsigned int trrdl_ps;
27 unsigned int tccdl_ps;
York Sun6db4fdd2018-01-29 09:44:35 -0800[diff] [blame]28 unsigned int trfc_slr_ps;
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]29#else
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]30 unsigned int twtr_ps; /* maximum = 63750 ps */
31 unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]32 = 511750 ps */
33
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]34 unsigned int trrd_ps; /* maximum = 63750 ps */
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]35 unsigned int trtp_ps; /* byte 38, spd->trtp */
36#endif
37 unsigned int twr_ps; /* maximum = 63750 ps */
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]38 unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]39
40 unsigned int refresh_rate_ps;
Valentin Longchamp0b810932013-10-18 11:47:20 +0200[diff] [blame]41 unsigned int extended_op_srt;
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]42
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]43#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]44 unsigned int tis_ps; /* byte 32, spd->ca_setup */
45 unsigned int tih_ps; /* byte 33, spd->ca_hold */
46 unsigned int tds_ps; /* byte 34, spd->data_setup */
47 unsigned int tdh_ps; /* byte 35, spd->data_hold */
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]48 unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */
49 unsigned int tqhs_ps; /* byte 45, spd->tqhs */
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]50#endif
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]51
52 unsigned int ndimms_present;
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]53 unsigned int lowest_common_spd_caslat;
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]54 unsigned int highest_common_derated_caslat;
55 unsigned int additive_latency;
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]56 unsigned int all_dimms_burst_lengths_bitmask;
57 unsigned int all_dimms_registered;
58 unsigned int all_dimms_unbuffered;
59 unsigned int all_dimms_ecc_capable;
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]60
61 unsigned long long total_mem;
62 unsigned long long base_address;
yorkde879322010-07-02 22:25:55 +0000[diff] [blame]63
64 /* DDR3 RDIMM */
65 unsigned char rcw[16]; /* Register Control Word 0-15 */
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]66} common_timing_params_t;
67
68#endif