blob: e4fa8a88565222560bb70c07db52641a804f3887 [file] [log] [blame]
Lokesh Vutlabc9979f2018-08-27 15:57:54 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
Nishanth Menoneaa39c62023-11-01 15:56:03 -05003 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutlabc9979f2018-08-27 15:57:54 +05304 *
5 * Texas Instruments' K3 SD Host Controller Interface
6 */
7
8#include <clk.h>
Lokesh Vutlabc9979f2018-08-27 15:57:54 +05309#include <dm.h>
10#include <malloc.h>
Faiz Abbas7a7e2c72021-02-04 15:10:53 +053011#include <mmc.h>
Lokesh Vutlabc9979f2018-08-27 15:57:54 +053012#include <power-domain.h>
Faiz Abbase9aed582019-06-11 00:43:38 +053013#include <regmap.h>
Lokesh Vutlabc9979f2018-08-27 15:57:54 +053014#include <sdhci.h>
Faiz Abbas2c2fc962021-02-04 15:10:50 +053015#include <soc.h>
Simon Glass9bc15642020-02-03 07:36:16 -070016#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060017#include <linux/bitops.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070018#include <linux/err.h>
Lokesh Vutlabc9979f2018-08-27 15:57:54 +053019
Faiz Abbase9aed582019-06-11 00:43:38 +053020/* CTL_CFG Registers */
21#define CTL_CFG_2 0x14
22
23#define SLOTTYPE_MASK GENMASK(31, 30)
24#define SLOTTYPE_EMBEDDED BIT(30)
25
26/* PHY Registers */
27#define PHY_CTRL1 0x100
28#define PHY_CTRL2 0x104
29#define PHY_CTRL3 0x108
30#define PHY_CTRL4 0x10C
31#define PHY_CTRL5 0x110
32#define PHY_CTRL6 0x114
33#define PHY_STAT1 0x130
34#define PHY_STAT2 0x134
35
36#define IOMUX_ENABLE_SHIFT 31
37#define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
38#define OTAPDLYENA_SHIFT 20
39#define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
40#define OTAPDLYSEL_SHIFT 12
41#define OTAPDLYSEL_MASK GENMASK(15, 12)
42#define STRBSEL_SHIFT 24
Faiz Abbas8cc051e2020-01-16 19:42:19 +053043#define STRBSEL_4BIT_MASK GENMASK(27, 24)
44#define STRBSEL_8BIT_MASK GENMASK(31, 24)
Faiz Abbase9aed582019-06-11 00:43:38 +053045#define SEL50_SHIFT 8
46#define SEL50_MASK BIT(SEL50_SHIFT)
47#define SEL100_SHIFT 9
48#define SEL100_MASK BIT(SEL100_SHIFT)
Faiz Abbas8cc051e2020-01-16 19:42:19 +053049#define FREQSEL_SHIFT 8
50#define FREQSEL_MASK GENMASK(10, 8)
Faiz Abbasc73f04e2021-02-04 15:10:52 +053051#define CLKBUFSEL_SHIFT 0
52#define CLKBUFSEL_MASK GENMASK(2, 0)
Faiz Abbase9aed582019-06-11 00:43:38 +053053#define DLL_TRIM_ICP_SHIFT 4
54#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
55#define DR_TY_SHIFT 20
56#define DR_TY_MASK GENMASK(22, 20)
57#define ENDLL_SHIFT 1
58#define ENDLL_MASK BIT(ENDLL_SHIFT)
59#define DLLRDY_SHIFT 0
60#define DLLRDY_MASK BIT(DLLRDY_SHIFT)
61#define PDB_SHIFT 0
62#define PDB_MASK BIT(PDB_SHIFT)
63#define CALDONE_SHIFT 1
64#define CALDONE_MASK BIT(CALDONE_SHIFT)
65#define RETRIM_SHIFT 17
66#define RETRIM_MASK BIT(RETRIM_SHIFT)
Faiz Abbasdef2a0f2021-02-04 15:10:51 +053067#define SELDLYTXCLK_SHIFT 17
68#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
69#define SELDLYRXCLK_SHIFT 16
70#define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
71#define ITAPDLYSEL_SHIFT 0
72#define ITAPDLYSEL_MASK GENMASK(4, 0)
73#define ITAPDLYENA_SHIFT 8
74#define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
75#define ITAPCHGWIN_SHIFT 9
76#define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
Faiz Abbase9aed582019-06-11 00:43:38 +053077
78#define DRIVER_STRENGTH_50_OHM 0x0
79#define DRIVER_STRENGTH_33_OHM 0x1
80#define DRIVER_STRENGTH_66_OHM 0x2
81#define DRIVER_STRENGTH_100_OHM 0x3
82#define DRIVER_STRENGTH_40_OHM 0x4
83
Faiz Abbasd8fb3092019-06-11 00:43:31 +053084#define AM654_SDHCI_MIN_FREQ 400000
Faiz Abbasdef2a0f2021-02-04 15:10:51 +053085#define CLOCK_TOO_SLOW_HZ 50000000
Lokesh Vutlabc9979f2018-08-27 15:57:54 +053086
Judith Mendez87bcbde2024-04-18 14:00:58 -050087#define ENABLE 0x1
88
Faiz Abbasd8fb3092019-06-11 00:43:31 +053089struct am654_sdhci_plat {
Lokesh Vutlabc9979f2018-08-27 15:57:54 +053090 struct mmc_config cfg;
91 struct mmc mmc;
Faiz Abbase9aed582019-06-11 00:43:38 +053092 struct regmap *base;
93 bool non_removable;
Faiz Abbas7101e122020-07-29 07:03:41 +053094 u32 otap_del_sel[MMC_MODES_END];
Faiz Abbasdef2a0f2021-02-04 15:10:51 +053095 u32 itap_del_sel[MMC_MODES_END];
Judith Mendez87bcbde2024-04-18 14:00:58 -050096 u32 itap_del_ena[MMC_MODES_END];
Faiz Abbase9aed582019-06-11 00:43:38 +053097 u32 trm_icp;
98 u32 drv_strength;
Faiz Abbas8cc051e2020-01-16 19:42:19 +053099 u32 strb_sel;
Faiz Abbasc73f04e2021-02-04 15:10:52 +0530100 u32 clkbuf_sel;
Faiz Abbasfd8be702019-06-13 10:29:51 +0530101 u32 flags;
Judith Mendez81c1d442024-04-18 14:00:56 -0500102 bool dll_enable;
Faiz Abbasb7f57bb2021-02-04 15:10:48 +0530103#define DLL_PRESENT BIT(0)
104#define IOMUX_PRESENT BIT(1)
105#define FREQSEL_2_BIT BIT(2)
106#define STRBSEL_4_BIT BIT(3)
Faiz Abbas947e8f32021-02-04 15:10:49 +0530107#define DLL_CALIB BIT(4)
Emanuele Ghidolifde0dff2024-07-02 21:54:29 +0200108 u32 quirks;
109#define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530110};
111
Faiz Abbasc6eb9e72020-02-26 13:44:33 +0530112struct timing_data {
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530113 const char *otap_binding;
114 const char *itap_binding;
Faiz Abbasc6eb9e72020-02-26 13:44:33 +0530115 u32 capability;
116};
117
Judith Mendez81c1d442024-04-18 14:00:56 -0500118struct window {
119 u8 start;
120 u8 end;
121 u8 length;
122};
123
Faiz Abbasc6eb9e72020-02-26 13:44:33 +0530124static const struct timing_data td[] = {
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530125 [MMC_LEGACY] = {"ti,otap-del-sel-legacy",
126 "ti,itap-del-sel-legacy",
127 0},
Judith Mendez14e6fb22025-04-17 18:43:31 -0500128 [MMC_HS] = {"ti,otap-del-sel-mmc-hs26",
129 "ti,itap-del-sel-mmc-hs26",
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530130 MMC_CAP(MMC_HS)},
131 [SD_HS] = {"ti,otap-del-sel-sd-hs",
132 "ti,itap-del-sel-sd-hs",
133 MMC_CAP(SD_HS)},
Judith Mendez14e6fb22025-04-17 18:43:31 -0500134 [MMC_HS_52] = {"ti,otap-del-sel-mmc-hs",
135 "ti,itap-del-sel-mmc-hs",
136 MMC_CAP(MMC_HS_52)},
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530137 [UHS_SDR12] = {"ti,otap-del-sel-sdr12",
138 "ti,itap-del-sel-sdr12",
139 MMC_CAP(UHS_SDR12)},
140 [UHS_SDR25] = {"ti,otap-del-sel-sdr25",
141 "ti,itap-del-sel-sdr25",
142 MMC_CAP(UHS_SDR25)},
143 [UHS_SDR50] = {"ti,otap-del-sel-sdr50",
144 NULL,
145 MMC_CAP(UHS_SDR50)},
146 [UHS_SDR104] = {"ti,otap-del-sel-sdr104",
147 NULL,
148 MMC_CAP(UHS_SDR104)},
149 [UHS_DDR50] = {"ti,otap-del-sel-ddr50",
150 NULL,
151 MMC_CAP(UHS_DDR50)},
152 [MMC_DDR_52] = {"ti,otap-del-sel-ddr52",
153 "ti,itap-del-sel-ddr52",
154 MMC_CAP(MMC_DDR_52)},
155 [MMC_HS_200] = {"ti,otap-del-sel-hs200",
156 NULL,
157 MMC_CAP(MMC_HS_200)},
158 [MMC_HS_400] = {"ti,otap-del-sel-hs400",
159 NULL,
160 MMC_CAP(MMC_HS_400)},
Faiz Abbasc6eb9e72020-02-26 13:44:33 +0530161};
162
Faiz Abbas8cc051e2020-01-16 19:42:19 +0530163struct am654_driver_data {
164 const struct sdhci_ops *ops;
165 u32 flags;
166};
167
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530168static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat,
169 unsigned int speed)
170{
171 int sel50, sel100, freqsel;
172 u32 mask, val;
173 int ret;
174
175 /* Disable delay chain mode */
176 regmap_update_bits(plat->base, PHY_CTRL5,
177 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
178
179 if (plat->flags & FREQSEL_2_BIT) {
180 switch (speed) {
181 case 200000000:
182 sel50 = 0;
183 sel100 = 0;
184 break;
185 case 100000000:
186 sel50 = 0;
187 sel100 = 1;
188 break;
189 default:
190 sel50 = 1;
191 sel100 = 0;
192 }
193
194 /* Configure PHY DLL frequency */
195 mask = SEL50_MASK | SEL100_MASK;
196 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
197 regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
198 } else {
199 switch (speed) {
200 case 200000000:
201 freqsel = 0x0;
202 break;
203 default:
204 freqsel = 0x4;
205 }
206 regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
207 freqsel << FREQSEL_SHIFT);
208 }
209
210 /* Configure DLL TRIM */
211 mask = DLL_TRIM_ICP_MASK;
212 val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
213
214 /* Configure DLL driver strength */
215 mask |= DR_TY_MASK;
216 val |= plat->drv_strength << DR_TY_SHIFT;
217 regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
218
219 /* Enable DLL */
220 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
221 0x1 << ENDLL_SHIFT);
222 /*
223 * Poll for DLL ready. Use a one second timeout.
224 * Works in all experiments done so far
225 */
226 ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
227 val & DLLRDY_MASK, 1000, 1000000);
228
229 return ret;
230}
231
232static void am654_sdhci_write_itapdly(struct am654_sdhci_plat *plat,
Judith Mendez87bcbde2024-04-18 14:00:58 -0500233 u32 itapdly, u32 enable)
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530234{
Judith Mendez87bcbde2024-04-18 14:00:58 -0500235 regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK,
236 enable << ITAPDLYENA_SHIFT);
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530237 /* Set ITAPCHGWIN before writing to ITAPDLY */
238 regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK,
239 1 << ITAPCHGWIN_SHIFT);
240 regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYSEL_MASK,
241 itapdly << ITAPDLYSEL_SHIFT);
242 regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
243}
244
245static void am654_sdhci_setup_delay_chain(struct am654_sdhci_plat *plat,
246 int mode)
247{
248 u32 mask, val;
249
250 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
251 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
252 regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
253
Judith Mendez87bcbde2024-04-18 14:00:58 -0500254 am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode],
255 plat->itap_del_ena[mode]);
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530256}
257
Faiz Abbase9aed582019-06-11 00:43:38 +0530258static int am654_sdhci_set_ios_post(struct sdhci_host *host)
259{
260 struct udevice *dev = host->mmc->dev;
Simon Glassfa20e932020-12-03 16:55:20 -0700261 struct am654_sdhci_plat *plat = dev_get_plat(dev);
Faiz Abbase9aed582019-06-11 00:43:38 +0530262 unsigned int speed = host->mmc->clock;
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530263 int mode = host->mmc->selected_mode;
Faiz Abbasc6eb9e72020-02-26 13:44:33 +0530264 u32 otap_del_sel;
Faiz Abbase9aed582019-06-11 00:43:38 +0530265 u32 mask, val;
266 int ret;
267
268 /* Reset SD Clock Enable */
269 val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
270 val &= ~SDHCI_CLOCK_CARD_EN;
271 sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
272
Faiz Abbas2c45a2c2021-02-04 15:10:47 +0530273 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
Faiz Abbase9aed582019-06-11 00:43:38 +0530274
275 /* restart clock */
276 sdhci_set_clock(host->mmc, speed);
277
278 /* switch phy back on */
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530279 otap_del_sel = plat->otap_del_sel[mode];
280 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
281 val = (1 << OTAPDLYENA_SHIFT) |
282 (otap_del_sel << OTAPDLYSEL_SHIFT);
Faiz Abbas8cc051e2020-01-16 19:42:19 +0530283
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530284 /* Write to STRBSEL for HS400 speed mode */
285 if (host->mmc->selected_mode == MMC_HS_400) {
286 if (plat->flags & STRBSEL_4_BIT)
287 mask |= STRBSEL_4BIT_MASK;
288 else
289 mask |= STRBSEL_8BIT_MASK;
Faiz Abbas8cc051e2020-01-16 19:42:19 +0530290
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530291 val |= plat->strb_sel << STRBSEL_SHIFT;
292 }
Faiz Abbas947e8f32021-02-04 15:10:49 +0530293
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530294 regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
Faiz Abbas947e8f32021-02-04 15:10:49 +0530295
Judith Mendezc9eb1dc2024-04-18 14:00:59 -0500296 if ((mode > UHS_SDR25 || mode == MMC_DDR_52) && speed >= CLOCK_TOO_SLOW_HZ) {
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530297 ret = am654_sdhci_setup_dll(plat, speed);
Faiz Abbase9aed582019-06-11 00:43:38 +0530298 if (ret)
299 return ret;
Judith Mendez81c1d442024-04-18 14:00:56 -0500300
301 plat->dll_enable = true;
Judith Mendez5d217152024-04-18 14:01:00 -0500302 if (mode == MMC_HS_400) {
303 plat->itap_del_ena[mode] = ENABLE;
304 plat->itap_del_sel[mode] = plat->itap_del_sel[mode - 1];
305 }
306
Judith Mendezc9eb1dc2024-04-18 14:00:59 -0500307 am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode],
308 plat->itap_del_ena[mode]);
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530309 } else {
310 am654_sdhci_setup_delay_chain(plat, mode);
Judith Mendez81c1d442024-04-18 14:00:56 -0500311 plat->dll_enable = false;
Faiz Abbase9aed582019-06-11 00:43:38 +0530312 }
313
Faiz Abbasc73f04e2021-02-04 15:10:52 +0530314 regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
315 plat->clkbuf_sel);
316
Faiz Abbase9aed582019-06-11 00:43:38 +0530317 return 0;
318}
319
Faiz Abbase9aed582019-06-11 00:43:38 +0530320int am654_sdhci_init(struct am654_sdhci_plat *plat)
321{
322 u32 ctl_cfg_2 = 0;
323 u32 mask, val;
324 int ret;
325
326 /* Reset OTAP to default value */
327 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
328 regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
329
Faiz Abbas947e8f32021-02-04 15:10:49 +0530330 if (plat->flags & DLL_CALIB) {
Faiz Abbasfd8be702019-06-13 10:29:51 +0530331 regmap_read(plat->base, PHY_STAT1, &val);
332 if (~val & CALDONE_MASK) {
333 /* Calibrate IO lines */
334 regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
335 PDB_MASK);
336 ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
337 val, val & CALDONE_MASK,
338 1, 20);
339 if (ret)
340 return ret;
341 }
Faiz Abbasfd8be702019-06-13 10:29:51 +0530342 }
Faiz Abbase9aed582019-06-11 00:43:38 +0530343
344 /* Enable pins by setting IO mux to 0 */
Faiz Abbas8cc051e2020-01-16 19:42:19 +0530345 if (plat->flags & IOMUX_PRESENT)
346 regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
Faiz Abbase9aed582019-06-11 00:43:38 +0530347
348 /* Set slot type based on SD or eMMC */
349 if (plat->non_removable)
350 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
351
352 regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
353
354 return 0;
355}
356
Faiz Abbase4425cb2020-02-26 13:44:34 +0530357#define MAX_SDCD_DEBOUNCE_TIME 2000
Emanuele Ghidolifde0dff2024-07-02 21:54:29 +0200358static int am654_sdhci_cd_poll(struct mmc *mmc)
Faiz Abbase4425cb2020-02-26 13:44:34 +0530359{
Faiz Abbase4425cb2020-02-26 13:44:34 +0530360 unsigned long start;
361 int val;
362
363 /*
364 * The controller takes about 1 second to debounce the card detect line
365 * and doesn't let us power on until that time is up. Instead of waiting
366 * for 1 second at every stage, poll on the CARD_PRESENT bit upto a
367 * maximum of 2 seconds to be safe..
368 */
369 start = get_timer(0);
370 do {
371 if (get_timer(start) > MAX_SDCD_DEBOUNCE_TIME)
372 return -ENOMEDIUM;
373
Emanuele Ghidolifde0dff2024-07-02 21:54:29 +0200374 val = mmc_getcd(mmc);
Faiz Abbase4425cb2020-02-26 13:44:34 +0530375 } while (!val);
376
Emanuele Ghidolifde0dff2024-07-02 21:54:29 +0200377 return 0;
378}
379
380static int am654_sdhci_deferred_probe(struct sdhci_host *host)
381{
382 struct udevice *dev = host->mmc->dev;
383 struct am654_sdhci_plat *plat = dev_get_plat(dev);
384 int ret;
385
386 if (!(plat->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST)) {
387 if (am654_sdhci_cd_poll(host->mmc))
388 return -ENOMEDIUM;
389 }
390
Faiz Abbase4425cb2020-02-26 13:44:34 +0530391 am654_sdhci_init(plat);
392
Emanuele Ghidolifde0dff2024-07-02 21:54:29 +0200393 ret = sdhci_probe(dev);
394
395 if (plat->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
396 u8 hostctrlreg = sdhci_readb(host, SDHCI_HOST_CONTROL);
397
398 hostctrlreg |= SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST;
399 sdhci_writeb(host, hostctrlreg, SDHCI_HOST_CONTROL);
400 }
401
402 return ret;
Faiz Abbase4425cb2020-02-26 13:44:34 +0530403}
404
Faiz Abbas36c8c5c2021-02-04 15:10:54 +0530405static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg)
406{
407 if (reg == SDHCI_HOST_CONTROL) {
408 switch (host->mmc->selected_mode) {
409 /*
410 * According to the data manual, HISPD bit
411 * should not be set in these speed modes.
412 */
413 case SD_HS:
414 case MMC_HS:
415 case UHS_SDR12:
416 case UHS_SDR25:
417 val &= ~SDHCI_CTRL_HISPD;
418 default:
419 break;
420 }
421 }
422
423 writeb(val, host->ioaddr + reg);
424}
Tom Rinidec7ea02024-05-20 13:35:03 -0600425#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
Judith Mendez81c1d442024-04-18 14:00:56 -0500426#define ITAPDLY_LENGTH 32
427#define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1)
428
429static u32 am654_sdhci_calculate_itap(struct udevice *dev, struct window
430 *fail_window, u8 num_fails, bool circular_buffer)
431{
432 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0;
433 u8 first_fail_start = 0, last_fail_end = 0;
434 struct window pass_window = {0, 0, 0};
435 int prev_fail_end = -1;
436 u8 i;
437
438 if (!num_fails)
439 return ITAPDLY_LAST_INDEX >> 1;
440
441 if (fail_window->length == ITAPDLY_LENGTH) {
442 dev_err(dev, "No passing ITAPDLY, return 0\n");
443 return 0;
444 }
445
446 first_fail_start = fail_window->start;
447 last_fail_end = fail_window[num_fails - 1].end;
448
449 for (i = 0; i < num_fails; i++) {
450 start_fail = fail_window[i].start;
451 end_fail = fail_window[i].end;
452 pass_length = start_fail - (prev_fail_end + 1);
453
454 if (pass_length > pass_window.length) {
455 pass_window.start = prev_fail_end + 1;
456 pass_window.length = pass_length;
457 }
458 prev_fail_end = end_fail;
459 }
460
461 if (!circular_buffer)
462 pass_length = ITAPDLY_LAST_INDEX - last_fail_end;
463 else
464 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start;
465
466 if (pass_length > pass_window.length) {
467 pass_window.start = last_fail_end + 1;
468 pass_window.length = pass_length;
469 }
470
471 if (!circular_buffer)
472 itap = pass_window.start + (pass_window.length >> 1);
473 else
474 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH;
475
476 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap;
477}
478
Faiz Abbas7a7e2c72021-02-04 15:10:53 +0530479static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
480{
481 struct udevice *dev = mmc->dev;
482 struct am654_sdhci_plat *plat = dev_get_plat(dev);
Judith Mendez81c1d442024-04-18 14:00:56 -0500483 struct window fail_window[ITAPDLY_LENGTH];
Judith Mendez87bcbde2024-04-18 14:00:58 -0500484 int mode = mmc->selected_mode;
Judith Mendez81c1d442024-04-18 14:00:56 -0500485 u8 curr_pass, itap;
486 u8 fail_index = 0;
487 u8 prev_pass = 1;
488
489 memset(fail_window, 0, sizeof(fail_window));
Faiz Abbas7a7e2c72021-02-04 15:10:53 +0530490
491 /* Enable ITAPDLY */
Judith Mendez87bcbde2024-04-18 14:00:58 -0500492 plat->itap_del_ena[mode] = ENABLE;
Faiz Abbas7a7e2c72021-02-04 15:10:53 +0530493
Judith Mendez81c1d442024-04-18 14:00:56 -0500494 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) {
Judith Mendez87bcbde2024-04-18 14:00:58 -0500495 am654_sdhci_write_itapdly(plat, itap, plat->itap_del_ena[mode]);
Faiz Abbas7a7e2c72021-02-04 15:10:53 +0530496
Judith Mendez81c1d442024-04-18 14:00:56 -0500497 curr_pass = !mmc_send_tuning(mmc, opcode);
498
499 if (!curr_pass && prev_pass)
500 fail_window[fail_index].start = itap;
Faiz Abbas7a7e2c72021-02-04 15:10:53 +0530501
Judith Mendez81c1d442024-04-18 14:00:56 -0500502 if (!curr_pass) {
503 fail_window[fail_index].end = itap;
504 fail_window[fail_index].length++;
505 }
506
507 if (curr_pass && !prev_pass)
508 fail_index++;
Faiz Abbas7a7e2c72021-02-04 15:10:53 +0530509
Judith Mendez81c1d442024-04-18 14:00:56 -0500510 prev_pass = curr_pass;
Faiz Abbas7a7e2c72021-02-04 15:10:53 +0530511 }
Judith Mendez81c1d442024-04-18 14:00:56 -0500512
513 if (fail_window[fail_index].length != 0)
514 fail_index++;
515
516 itap = am654_sdhci_calculate_itap(dev, fail_window, fail_index,
517 plat->dll_enable);
518
Judith Mendez5d217152024-04-18 14:01:00 -0500519 /* Save ITAPDLY */
520 plat->itap_del_sel[mode] = itap;
521
Judith Mendez87bcbde2024-04-18 14:00:58 -0500522 am654_sdhci_write_itapdly(plat, itap, plat->itap_del_ena[mode]);
Faiz Abbas7a7e2c72021-02-04 15:10:53 +0530523
524 return 0;
525}
526#endif
Faiz Abbase4425cb2020-02-26 13:44:34 +0530527const struct sdhci_ops am654_sdhci_ops = {
Tom Rinidec7ea02024-05-20 13:35:03 -0600528#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
Faiz Abbas7a7e2c72021-02-04 15:10:53 +0530529 .platform_execute_tuning = am654_sdhci_execute_tuning,
530#endif
Faiz Abbase4425cb2020-02-26 13:44:34 +0530531 .deferred_probe = am654_sdhci_deferred_probe,
532 .set_ios_post = &am654_sdhci_set_ios_post,
Faiz Abbas9c10cfe2021-02-04 15:10:55 +0530533 .set_control_reg = sdhci_set_control_reg,
Faiz Abbas36c8c5c2021-02-04 15:10:54 +0530534 .write_b = am654_sdhci_write_b,
Faiz Abbase4425cb2020-02-26 13:44:34 +0530535};
536
537const struct am654_driver_data am654_drv_data = {
538 .ops = &am654_sdhci_ops,
Faiz Abbas2c2fc962021-02-04 15:10:50 +0530539 .flags = DLL_PRESENT | IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT,
540};
541
542const struct am654_driver_data am654_sr1_drv_data = {
543 .ops = &am654_sdhci_ops,
Faiz Abbas947e8f32021-02-04 15:10:49 +0530544 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | DLL_CALIB |
545 STRBSEL_4_BIT,
Faiz Abbase4425cb2020-02-26 13:44:34 +0530546};
547
548const struct am654_driver_data j721e_8bit_drv_data = {
549 .ops = &am654_sdhci_ops,
Faiz Abbas947e8f32021-02-04 15:10:49 +0530550 .flags = DLL_PRESENT | DLL_CALIB,
Faiz Abbase4425cb2020-02-26 13:44:34 +0530551};
552
553static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
554{
555 struct udevice *dev = host->mmc->dev;
Simon Glassfa20e932020-12-03 16:55:20 -0700556 struct am654_sdhci_plat *plat = dev_get_plat(dev);
Nitin Yadav83db1f92024-04-18 14:00:57 -0500557 int mode = host->mmc->selected_mode;
558 u32 otap_del_sel;
Judith Mendez87bcbde2024-04-18 14:00:58 -0500559 u32 itap_del_ena;
Nitin Yadav83db1f92024-04-18 14:00:57 -0500560 u32 itap_del_sel;
561 u32 mask, val;
Faiz Abbase4425cb2020-02-26 13:44:34 +0530562
Nitin Yadav83db1f92024-04-18 14:00:57 -0500563 otap_del_sel = plat->otap_del_sel[mode];
564
Faiz Abbase4425cb2020-02-26 13:44:34 +0530565 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
Nitin Yadav83db1f92024-04-18 14:00:57 -0500566 val = (1 << OTAPDLYENA_SHIFT) |
567 (otap_del_sel << OTAPDLYSEL_SHIFT);
568
Judith Mendez87bcbde2024-04-18 14:00:58 -0500569 itap_del_ena = plat->itap_del_ena[mode];
Nitin Yadav83db1f92024-04-18 14:00:57 -0500570 itap_del_sel = plat->itap_del_sel[mode];
571
572 mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK;
Judith Mendez87bcbde2024-04-18 14:00:58 -0500573 val |= (itap_del_ena << ITAPDLYENA_SHIFT) |
Nitin Yadav83db1f92024-04-18 14:00:57 -0500574 (itap_del_sel << ITAPDLYSEL_SHIFT);
575
576 regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK,
577 1 << ITAPCHGWIN_SHIFT);
Faiz Abbase4425cb2020-02-26 13:44:34 +0530578 regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
Nitin Yadav83db1f92024-04-18 14:00:57 -0500579 regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
Faiz Abbase4425cb2020-02-26 13:44:34 +0530580
Faiz Abbasc73f04e2021-02-04 15:10:52 +0530581 regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
582 plat->clkbuf_sel);
583
Faiz Abbase4425cb2020-02-26 13:44:34 +0530584 return 0;
585}
586
587const struct sdhci_ops j721e_4bit_sdhci_ops = {
Tom Rinidec7ea02024-05-20 13:35:03 -0600588#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
Faiz Abbas7a7e2c72021-02-04 15:10:53 +0530589 .platform_execute_tuning = am654_sdhci_execute_tuning,
590#endif
Faiz Abbase4425cb2020-02-26 13:44:34 +0530591 .deferred_probe = am654_sdhci_deferred_probe,
592 .set_ios_post = &j721e_4bit_sdhci_set_ios_post,
Faiz Abbas9c10cfe2021-02-04 15:10:55 +0530593 .set_control_reg = sdhci_set_control_reg,
Faiz Abbas36c8c5c2021-02-04 15:10:54 +0530594 .write_b = am654_sdhci_write_b,
Faiz Abbase4425cb2020-02-26 13:44:34 +0530595};
596
597const struct am654_driver_data j721e_4bit_drv_data = {
598 .ops = &j721e_4bit_sdhci_ops,
599 .flags = IOMUX_PRESENT,
600};
601
Dave Gerlach057d6af2021-04-23 11:27:40 -0500602static const struct am654_driver_data sdhci_am64_8bit_drvdata = {
603 .ops = &am654_sdhci_ops,
604 .flags = DLL_PRESENT | DLL_CALIB,
605};
606
607static const struct am654_driver_data sdhci_am64_4bit_drvdata = {
608 .ops = &j721e_4bit_sdhci_ops,
609 .flags = IOMUX_PRESENT,
610};
611
Faiz Abbas2c2fc962021-02-04 15:10:50 +0530612const struct soc_attr am654_sdhci_soc_attr[] = {
613 { .family = "AM65X", .revision = "SR1.0", .data = &am654_sr1_drv_data},
614 {/* sentinel */}
615};
616
Faiz Abbasc6eb9e72020-02-26 13:44:33 +0530617static int sdhci_am654_get_otap_delay(struct udevice *dev,
618 struct mmc_config *cfg)
619{
Simon Glassfa20e932020-12-03 16:55:20 -0700620 struct am654_sdhci_plat *plat = dev_get_plat(dev);
Faiz Abbasc6eb9e72020-02-26 13:44:33 +0530621 int ret;
622 int i;
623
624 /* ti,otap-del-sel-legacy is mandatory */
625 ret = dev_read_u32(dev, "ti,otap-del-sel-legacy",
626 &plat->otap_del_sel[0]);
627 if (ret)
628 return ret;
629 /*
630 * Remove the corresponding capability if an otap-del-sel
631 * value is not found
632 */
Nitin Yadav83db1f92024-04-18 14:00:57 -0500633 for (i = MMC_LEGACY; i <= MMC_HS_400; i++) {
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530634 ret = dev_read_u32(dev, td[i].otap_binding,
635 &plat->otap_del_sel[i]);
Faiz Abbasc6eb9e72020-02-26 13:44:33 +0530636 if (ret) {
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530637 dev_dbg(dev, "Couldn't find %s\n", td[i].otap_binding);
Faiz Abbasc6eb9e72020-02-26 13:44:33 +0530638 /*
639 * Remove the corresponding capability
640 * if an otap-del-sel value is not found
641 */
642 cfg->host_caps &= ~td[i].capability;
643 }
Faiz Abbasdef2a0f2021-02-04 15:10:51 +0530644
Judith Mendez87bcbde2024-04-18 14:00:58 -0500645 if (td[i].itap_binding) {
646 ret = dev_read_u32(dev, td[i].itap_binding,
647 &plat->itap_del_sel[i]);
648
649 if (!ret)
650 plat->itap_del_ena[i] = ENABLE;
651 }
Faiz Abbasc6eb9e72020-02-26 13:44:33 +0530652 }
653
654 return 0;
655}
656
Faiz Abbasd8fb3092019-06-11 00:43:31 +0530657static int am654_sdhci_probe(struct udevice *dev)
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530658{
Faiz Abbas8cc051e2020-01-16 19:42:19 +0530659 struct am654_driver_data *drv_data =
660 (struct am654_driver_data *)dev_get_driver_data(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700661 struct am654_sdhci_plat *plat = dev_get_plat(dev);
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530662 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
663 struct sdhci_host *host = dev_get_priv(dev);
Faiz Abbase9aed582019-06-11 00:43:38 +0530664 struct mmc_config *cfg = &plat->cfg;
Faiz Abbas2c2fc962021-02-04 15:10:50 +0530665 const struct soc_attr *soc;
666 const struct am654_driver_data *soc_drv_data;
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530667 struct clk clk;
668 unsigned long clock;
669 int ret;
670
Faiz Abbasdc2bcc22020-01-16 19:42:18 +0530671 ret = clk_get_by_name(dev, "clk_xin", &clk);
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530672 if (ret) {
673 dev_err(dev, "failed to get clock\n");
674 return ret;
675 }
676
677 clock = clk_get_rate(&clk);
678 if (IS_ERR_VALUE(clock)) {
679 dev_err(dev, "failed to get rate\n");
680 return clock;
681 }
682
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530683 host->max_clk = clock;
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530684 host->mmc = &plat->mmc;
Faiz Abbase9aed582019-06-11 00:43:38 +0530685 host->mmc->dev = dev;
Faiz Abbas36c8c5c2021-02-04 15:10:54 +0530686 host->ops = drv_data->ops;
Faiz Abbase9aed582019-06-11 00:43:38 +0530687 ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
688 AM654_SDHCI_MIN_FREQ);
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530689 if (ret)
690 return ret;
Faiz Abbas8cc051e2020-01-16 19:42:19 +0530691
Faiz Abbasc6eb9e72020-02-26 13:44:33 +0530692 ret = sdhci_am654_get_otap_delay(dev, cfg);
693 if (ret)
694 return ret;
695
Faiz Abbas2c2fc962021-02-04 15:10:50 +0530696 /* Update ops based on SoC revision */
697 soc = soc_device_match(am654_sdhci_soc_attr);
698 if (soc && soc->data) {
699 soc_drv_data = soc->data;
700 host->ops = soc_drv_data->ops;
701 }
702
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530703 host->mmc->priv = host;
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530704 upriv->mmc = host->mmc;
705
Faiz Abbase9aed582019-06-11 00:43:38 +0530706 regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
707
Emanuele Ghidolifde0dff2024-07-02 21:54:29 +0200708 if (plat->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST)
709 am654_sdhci_deferred_probe(host);
710
Faiz Abbase4425cb2020-02-26 13:44:34 +0530711 return 0;
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530712}
713
Simon Glassaad29ae2020-12-03 16:55:21 -0700714static int am654_sdhci_of_to_plat(struct udevice *dev)
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530715{
Simon Glassfa20e932020-12-03 16:55:20 -0700716 struct am654_sdhci_plat *plat = dev_get_plat(dev);
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530717 struct sdhci_host *host = dev_get_priv(dev);
Faiz Abbase9aed582019-06-11 00:43:38 +0530718 struct mmc_config *cfg = &plat->cfg;
719 u32 drv_strength;
720 int ret;
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530721
722 host->name = dev->name;
Johan Jonker8d5d8e02023-03-13 01:32:04 +0100723 host->ioaddr = dev_read_addr_ptr(dev);
Faiz Abbase9aed582019-06-11 00:43:38 +0530724 plat->non_removable = dev_read_bool(dev, "non-removable");
725
Faiz Abbasfd8be702019-06-13 10:29:51 +0530726 if (plat->flags & DLL_PRESENT) {
727 ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
728 if (ret)
729 return ret;
730
731 ret = dev_read_u32(dev, "ti,driver-strength-ohm",
732 &drv_strength);
733 if (ret)
734 return ret;
Faiz Abbase9aed582019-06-11 00:43:38 +0530735
Faiz Abbasfd8be702019-06-13 10:29:51 +0530736 switch (drv_strength) {
737 case 50:
738 plat->drv_strength = DRIVER_STRENGTH_50_OHM;
739 break;
740 case 33:
741 plat->drv_strength = DRIVER_STRENGTH_33_OHM;
742 break;
743 case 66:
744 plat->drv_strength = DRIVER_STRENGTH_66_OHM;
745 break;
746 case 100:
747 plat->drv_strength = DRIVER_STRENGTH_100_OHM;
748 break;
749 case 40:
750 plat->drv_strength = DRIVER_STRENGTH_40_OHM;
751 break;
752 default:
753 dev_err(dev, "Invalid driver strength\n");
754 return -EINVAL;
755 }
Faiz Abbase9aed582019-06-11 00:43:38 +0530756 }
757
Aswath Govindraju4509fb62021-05-25 15:08:23 +0530758 dev_read_u32(dev, "ti,strobe-sel", &plat->strb_sel);
Faiz Abbasc73f04e2021-02-04 15:10:52 +0530759 dev_read_u32(dev, "ti,clkbuf-sel", &plat->clkbuf_sel);
Emanuele Ghidolifde0dff2024-07-02 21:54:29 +0200760 if (dev_read_bool(dev, "ti,fails-without-test-cd"))
761 plat->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
Faiz Abbasc73f04e2021-02-04 15:10:52 +0530762
Faiz Abbase9aed582019-06-11 00:43:38 +0530763 ret = mmc_of_parse(dev, cfg);
764 if (ret)
765 return ret;
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530766
767 return 0;
768}
769
Faiz Abbasd8fb3092019-06-11 00:43:31 +0530770static int am654_sdhci_bind(struct udevice *dev)
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530771{
Faiz Abbas8cc051e2020-01-16 19:42:19 +0530772 struct am654_driver_data *drv_data =
773 (struct am654_driver_data *)dev_get_driver_data(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700774 struct am654_sdhci_plat *plat = dev_get_plat(dev);
Faiz Abbas2c2fc962021-02-04 15:10:50 +0530775 const struct soc_attr *soc;
776 const struct am654_driver_data *soc_drv_data;
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530777
Faiz Abbas8cc051e2020-01-16 19:42:19 +0530778 plat->flags = drv_data->flags;
779
Faiz Abbas2c2fc962021-02-04 15:10:50 +0530780 /* Update flags based on SoC revision */
781 soc = soc_device_match(am654_sdhci_soc_attr);
782 if (soc && soc->data) {
783 soc_drv_data = soc->data;
784 plat->flags = soc_drv_data->flags;
785 }
786
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530787 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
788}
789
Faiz Abbasd8fb3092019-06-11 00:43:31 +0530790static const struct udevice_id am654_sdhci_ids[] = {
Faiz Abbasfd8be702019-06-13 10:29:51 +0530791 {
792 .compatible = "ti,am654-sdhci-5.1",
Faiz Abbas8cc051e2020-01-16 19:42:19 +0530793 .data = (ulong)&am654_drv_data,
Faiz Abbasfd8be702019-06-13 10:29:51 +0530794 },
795 {
796 .compatible = "ti,j721e-sdhci-8bit",
Faiz Abbas8cc051e2020-01-16 19:42:19 +0530797 .data = (ulong)&j721e_8bit_drv_data,
Faiz Abbasfd8be702019-06-13 10:29:51 +0530798 },
799 {
800 .compatible = "ti,j721e-sdhci-4bit",
Faiz Abbas8cc051e2020-01-16 19:42:19 +0530801 .data = (ulong)&j721e_4bit_drv_data,
Faiz Abbasfd8be702019-06-13 10:29:51 +0530802 },
Dave Gerlach057d6af2021-04-23 11:27:40 -0500803 {
804 .compatible = "ti,am64-sdhci-8bit",
805 .data = (ulong)&sdhci_am64_8bit_drvdata,
806 },
807 {
808 .compatible = "ti,am64-sdhci-4bit",
809 .data = (ulong)&sdhci_am64_4bit_drvdata,
810 },
Aswath Govindraju71b9a7b2022-05-25 13:38:39 +0530811 {
812 .compatible = "ti,am62-sdhci",
813 .data = (ulong)&sdhci_am64_4bit_drvdata,
814 },
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530815 { }
816};
817
Faiz Abbasd8fb3092019-06-11 00:43:31 +0530818U_BOOT_DRIVER(am654_sdhci_drv) = {
819 .name = "am654_sdhci",
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530820 .id = UCLASS_MMC,
Faiz Abbasd8fb3092019-06-11 00:43:31 +0530821 .of_match = am654_sdhci_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700822 .of_to_plat = am654_sdhci_of_to_plat,
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530823 .ops = &sdhci_ops,
Faiz Abbasd8fb3092019-06-11 00:43:31 +0530824 .bind = am654_sdhci_bind,
825 .probe = am654_sdhci_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700826 .priv_auto = sizeof(struct sdhci_host),
Simon Glass71fa5b42020-12-03 16:55:18 -0700827 .plat_auto = sizeof(struct am654_sdhci_plat),
Lokesh Vutlabc9979f2018-08-27 15:57:54 +0530828};