blob: f481521a0fe0cbb9490d148c0f0a0ff998acb315 [file] [log] [blame]
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +09001/*
2 * Device Tree Source for UniPhier PH1-sLD3 SoC
3 *
Masahiro Yamadabbbb0bd2015-06-30 18:27:00 +09004 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +09005 *
Masahiro Yamada7bfb0a22015-06-30 18:27:01 +09006 * SPDX-License-Identifier: GPL-2.0+ X11
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +09007 */
8
9/include/ "skeleton.dtsi"
10
11/ {
Masahiro Yamadad5f83a42015-03-11 15:54:46 +090012 compatible = "socionext,ph1-sld3";
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +090013
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
Masahiro Yamadabbbb0bd2015-06-30 18:27:00 +090017 enable-method = "socionext,uniphier-smp";
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +090018
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
23 };
24
25 cpu@1 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <1>;
29 };
30 };
31
Masahiro Yamadabbbb0bd2015-06-30 18:27:00 +090032 clocks {
33 arm_timer_clk: arm_timer_clk {
34 #clock-cells = <0>;
35 compatible = "fixed-clock";
36 clock-frequency = <50000000>;
37 };
Masahiro Yamada37649af2015-08-28 22:33:13 +090038
39 uart_clk: uart_clk {
40 #clock-cells = <0>;
41 compatible = "fixed-clock";
42 clock-frequency = <36864000>;
43 };
44
45 iobus_clk: iobus_clk {
46 #clock-cells = <0>;
47 compatible = "fixed-clock";
48 clock-frequency = <100000000>;
49 };
Masahiro Yamadabbbb0bd2015-06-30 18:27:00 +090050 };
51
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +090052 soc {
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges;
Masahiro Yamadabbbb0bd2015-06-30 18:27:00 +090057 interrupt-parent = <&intc>;
58
59 extbus: extbus {
60 compatible = "simple-bus";
61 #address-cells = <2>;
62 #size-cells = <1>;
63 };
64
65 timer@20000200 {
66 compatible = "arm,cortex-a9-global-timer";
67 reg = <0x20000200 0x20>;
68 interrupts = <1 11 0x304>;
69 clocks = <&arm_timer_clk>;
70 };
71
72 timer@20000600 {
73 compatible = "arm,cortex-a9-twd-timer";
74 reg = <0x20000600 0x20>;
75 interrupts = <1 13 0x304>;
76 clocks = <&arm_timer_clk>;
77 };
78
79 intc: interrupt-controller@20001000 {
80 compatible = "arm,cortex-a9-gic";
81 #interrupt-cells = <3>;
82 interrupt-controller;
83 reg = <0x20001000 0x1000>,
84 <0x20000100 0x100>;
85 };
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +090086
Masahiro Yamada37649af2015-08-28 22:33:13 +090087 serial0: serial@54006800 {
Masahiro Yamadad5f83a42015-03-11 15:54:46 +090088 compatible = "socionext,uniphier-uart";
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +090089 status = "disabled";
Masahiro Yamada37649af2015-08-28 22:33:13 +090090 reg = <0x54006800 0x40>;
91 interrupts = <0 33 4>;
92 clocks = <&uart_clk>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +090093 clock-frequency = <36864000>;
94 };
95
Masahiro Yamada37649af2015-08-28 22:33:13 +090096 serial1: serial@54006900 {
Masahiro Yamadad5f83a42015-03-11 15:54:46 +090097 compatible = "socionext,uniphier-uart";
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +090098 status = "disabled";
Masahiro Yamada37649af2015-08-28 22:33:13 +090099 reg = <0x54006900 0x40>;
100 interrupts = <0 35 4>;
101 clocks = <&uart_clk>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900102 clock-frequency = <36864000>;
103 };
104
Masahiro Yamada37649af2015-08-28 22:33:13 +0900105 serial2: serial@54006a00 {
Masahiro Yamadad5f83a42015-03-11 15:54:46 +0900106 compatible = "socionext,uniphier-uart";
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900107 status = "disabled";
Masahiro Yamada37649af2015-08-28 22:33:13 +0900108 reg = <0x54006a00 0x40>;
109 interrupts = <0 37 4>;
110 clocks = <&uart_clk>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900111 clock-frequency = <36864000>;
112 };
113
114 i2c0: i2c@58400000 {
Masahiro Yamadad5f83a42015-03-11 15:54:46 +0900115 compatible = "socionext,uniphier-i2c";
Masahiro Yamada37649af2015-08-28 22:33:13 +0900116 status = "disabled";
117 reg = <0x58400000 0x40>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900118 #address-cells = <1>;
119 #size-cells = <0>;
Masahiro Yamada37649af2015-08-28 22:33:13 +0900120 interrupts = <0 41 1>;
121 clocks = <&iobus_clk>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900122 clock-frequency = <100000>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900123 };
124
125 i2c1: i2c@58480000 {
Masahiro Yamadad5f83a42015-03-11 15:54:46 +0900126 compatible = "socionext,uniphier-i2c";
Masahiro Yamada37649af2015-08-28 22:33:13 +0900127 status = "disabled";
128 reg = <0x58480000 0x40>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900129 #address-cells = <1>;
130 #size-cells = <0>;
Masahiro Yamada37649af2015-08-28 22:33:13 +0900131 interrupts = <0 42 1>;
132 clocks = <&iobus_clk>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900133 clock-frequency = <100000>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900134 };
135
136 i2c2: i2c@58500000 {
Masahiro Yamadad5f83a42015-03-11 15:54:46 +0900137 compatible = "socionext,uniphier-i2c";
Masahiro Yamada37649af2015-08-28 22:33:13 +0900138 status = "disabled";
139 reg = <0x58500000 0x40>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900140 #address-cells = <1>;
141 #size-cells = <0>;
Masahiro Yamada37649af2015-08-28 22:33:13 +0900142 interrupts = <0 43 1>;
143 clocks = <&iobus_clk>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900144 clock-frequency = <100000>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900145 };
146
147 i2c3: i2c@58580000 {
Masahiro Yamadad5f83a42015-03-11 15:54:46 +0900148 compatible = "socionext,uniphier-i2c";
Masahiro Yamada37649af2015-08-28 22:33:13 +0900149 status = "disabled";
150 reg = <0x58580000 0x40>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900151 #address-cells = <1>;
152 #size-cells = <0>;
Masahiro Yamada37649af2015-08-28 22:33:13 +0900153 interrupts = <0 44 1>;
154 clocks = <&iobus_clk>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900155 clock-frequency = <100000>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900156 };
157
Masahiro Yamada37649af2015-08-28 22:33:13 +0900158 /* chip-internal connection for DMD */
Masahiro Yamada3e278952015-07-21 14:04:23 +0900159 i2c4: i2c@58600000 {
Masahiro Yamada37649af2015-08-28 22:33:13 +0900160 compatible = "socionext,uniphier-i2c";
161 reg = <0x58600000 0x40>;
Masahiro Yamada3e278952015-07-21 14:04:23 +0900162 #address-cells = <1>;
163 #size-cells = <0>;
Masahiro Yamada37649af2015-08-28 22:33:13 +0900164 interrupts = <0 45 1>;
165 clocks = <&iobus_clk>;
Masahiro Yamada3e278952015-07-21 14:04:23 +0900166 clock-frequency = <400000>;
Masahiro Yamada3e278952015-07-21 14:04:23 +0900167 };
168
Masahiro Yamadabbbb0bd2015-06-30 18:27:00 +0900169 system-bus-controller-misc@59800000 {
170 compatible = "socionext,uniphier-system-bus-controller-misc",
171 "syscon";
172 reg = <0x59800000 0x2000>;
173 };
174
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900175 usb0: usb@5a800100 {
Masahiro Yamadad5f83a42015-03-11 15:54:46 +0900176 compatible = "socionext,uniphier-ehci", "generic-ehci";
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900177 status = "disabled";
178 reg = <0x5a800100 0x100>;
Masahiro Yamada37649af2015-08-28 22:33:13 +0900179 interrupts = <0 80 4>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900180 };
181
182 usb1: usb@5a810100 {
Masahiro Yamadad5f83a42015-03-11 15:54:46 +0900183 compatible = "socionext,uniphier-ehci", "generic-ehci";
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900184 status = "disabled";
185 reg = <0x5a810100 0x100>;
Masahiro Yamada37649af2015-08-28 22:33:13 +0900186 interrupts = <0 81 4>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900187 };
188
189 usb2: usb@5a820100 {
Masahiro Yamadad5f83a42015-03-11 15:54:46 +0900190 compatible = "socionext,uniphier-ehci", "generic-ehci";
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900191 status = "disabled";
192 reg = <0x5a820100 0x100>;
Masahiro Yamada37649af2015-08-28 22:33:13 +0900193 interrupts = <0 82 4>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900194 };
195
196 usb3: usb@5a830100 {
Masahiro Yamadad5f83a42015-03-11 15:54:46 +0900197 compatible = "socionext,uniphier-ehci", "generic-ehci";
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900198 status = "disabled";
199 reg = <0x5a830100 0x100>;
Masahiro Yamada37649af2015-08-28 22:33:13 +0900200 interrupts = <0 83 4>;
Masahiro Yamadaa90ca9a2014-12-06 00:03:24 +0900201 };
202
203 nand: nand@f8000000 {
204 compatible = "denali,denali-nand-dt";
205 reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
206 reg-names = "nand_data", "denali_reg";
207 };
208 };
209};