Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2014 - 2015 Xilinx, Inc. |
Michal Simek | a8c9436 | 2023-07-10 14:35:49 +0200 | [diff] [blame] | 4 | * Michal Simek <michal.simek@amd.com> |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_ARCH_SYS_PROTO_H |
| 8 | #define _ASM_ARCH_SYS_PROTO_H |
| 9 | |
Siva Durga Prasad Paladugu | 9f0a8e9 | 2017-07-25 11:51:36 +0530 | [diff] [blame] | 10 | #define ZYNQMP_CSU_SILICON_VER_MASK 0xF |
Siva Durga Prasad Paladugu | b1acb65 | 2018-02-28 13:26:53 +0530 | [diff] [blame] | 11 | #define KEY_PTR_LEN 32 |
Siva Durga Prasad Paladugu | 8b75ad6 | 2018-09-06 16:34:44 +0530 | [diff] [blame] | 12 | #define IV_SIZE 12 |
T Karthik Reddy | 59ec641 | 2019-01-07 17:05:10 +0530 | [diff] [blame] | 13 | #define RSA_KEY_SIZE 512 |
| 14 | #define MODULUS_LEN 512 |
| 15 | #define PRIV_EXPO_LEN 512 |
| 16 | #define PUB_EXPO_LEN 4 |
Siva Durga Prasad Paladugu | 9f0a8e9 | 2017-07-25 11:51:36 +0530 | [diff] [blame] | 17 | |
T Karthik Reddy | 89cbce9 | 2019-01-07 17:05:11 +0530 | [diff] [blame] | 18 | #define ZYNQMP_SHA3_INIT 1 |
| 19 | #define ZYNQMP_SHA3_UPDATE 2 |
| 20 | #define ZYNQMP_SHA3_FINAL 4 |
| 21 | #define ZYNQMP_SHA3_SIZE 48 |
| 22 | |
Siva Durga Prasad Paladugu | 6809e81 | 2018-05-31 15:10:23 +0530 | [diff] [blame] | 23 | #define ZYNQMP_FPGA_BIT_AUTH_DDR 1 |
| 24 | #define ZYNQMP_FPGA_BIT_AUTH_OCM 2 |
| 25 | #define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3 |
| 26 | #define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4 |
Siva Durga Prasad Paladugu | 91c315d | 2018-03-01 17:44:47 +0530 | [diff] [blame] | 27 | #define ZYNQMP_FPGA_BIT_NS 5 |
| 28 | |
Siva Durga Prasad Paladugu | 6809e81 | 2018-05-31 15:10:23 +0530 | [diff] [blame] | 29 | #define ZYNQMP_FPGA_AUTH_DDR 1 |
| 30 | |
Siva Durga Prasad Paladugu | 9f0a8e9 | 2017-07-25 11:51:36 +0530 | [diff] [blame] | 31 | enum { |
| 32 | IDCODE, |
| 33 | VERSION, |
Michal Simek | 50d8cef | 2017-08-22 14:58:53 +0200 | [diff] [blame] | 34 | IDCODE2, |
Siva Durga Prasad Paladugu | 9f0a8e9 | 2017-07-25 11:51:36 +0530 | [diff] [blame] | 35 | }; |
| 36 | |
| 37 | enum { |
| 38 | ZYNQMP_SILICON_V1, |
| 39 | ZYNQMP_SILICON_V2, |
| 40 | ZYNQMP_SILICON_V3, |
| 41 | ZYNQMP_SILICON_V4, |
| 42 | }; |
| 43 | |
Siva Durga Prasad Paladugu | 5e2a907 | 2017-07-13 19:01:09 +0530 | [diff] [blame] | 44 | enum { |
| 45 | TCM_LOCK, |
| 46 | TCM_SPLIT, |
| 47 | }; |
| 48 | |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 49 | unsigned int zynqmp_get_silicon_version(void); |
| 50 | |
Siva Durga Prasad Paladugu | 5e2a907 | 2017-07-13 19:01:09 +0530 | [diff] [blame] | 51 | void initialize_tcm(bool mode); |
Nitin Jain | 9bcc76f | 2018-04-20 12:30:40 +0530 | [diff] [blame] | 52 | void mem_map_fill(void); |
Siva Durga Prasad Paladugu | 48eaa0c | 2018-10-05 15:09:05 +0530 | [diff] [blame] | 53 | #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) |
| 54 | void tcm_init(u8 mode); |
| 55 | #endif |
Siva Durga Prasad Paladugu | cd35d52 | 2017-07-25 11:51:38 +0530 | [diff] [blame] | 56 | |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 57 | #endif /* _ASM_ARCH_SYS_PROTO_H */ |