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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simek04b7e622015-01-15 10:01:51 +01002/*
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
Michal Simeka8c94362023-07-10 14:35:49 +02004 * Michal Simek <michal.simek@amd.com>
Michal Simek04b7e622015-01-15 10:01:51 +01005 */
6
7#ifndef _ASM_ARCH_SYS_PROTO_H
8#define _ASM_ARCH_SYS_PROTO_H
9
Siva Durga Prasad Paladugu9f0a8e92017-07-25 11:51:36 +053010#define ZYNQMP_CSU_SILICON_VER_MASK 0xF
Siva Durga Prasad Paladugub1acb652018-02-28 13:26:53 +053011#define KEY_PTR_LEN 32
Siva Durga Prasad Paladugu8b75ad62018-09-06 16:34:44 +053012#define IV_SIZE 12
T Karthik Reddy59ec6412019-01-07 17:05:10 +053013#define RSA_KEY_SIZE 512
14#define MODULUS_LEN 512
15#define PRIV_EXPO_LEN 512
16#define PUB_EXPO_LEN 4
Siva Durga Prasad Paladugu9f0a8e92017-07-25 11:51:36 +053017
T Karthik Reddy89cbce92019-01-07 17:05:11 +053018#define ZYNQMP_SHA3_INIT 1
19#define ZYNQMP_SHA3_UPDATE 2
20#define ZYNQMP_SHA3_FINAL 4
21#define ZYNQMP_SHA3_SIZE 48
22
Siva Durga Prasad Paladugu6809e812018-05-31 15:10:23 +053023#define ZYNQMP_FPGA_BIT_AUTH_DDR 1
24#define ZYNQMP_FPGA_BIT_AUTH_OCM 2
25#define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3
26#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4
Siva Durga Prasad Paladugu91c315d2018-03-01 17:44:47 +053027#define ZYNQMP_FPGA_BIT_NS 5
28
Siva Durga Prasad Paladugu6809e812018-05-31 15:10:23 +053029#define ZYNQMP_FPGA_AUTH_DDR 1
30
Siva Durga Prasad Paladugu9f0a8e92017-07-25 11:51:36 +053031enum {
32 IDCODE,
33 VERSION,
Michal Simek50d8cef2017-08-22 14:58:53 +020034 IDCODE2,
Siva Durga Prasad Paladugu9f0a8e92017-07-25 11:51:36 +053035};
36
37enum {
38 ZYNQMP_SILICON_V1,
39 ZYNQMP_SILICON_V2,
40 ZYNQMP_SILICON_V3,
41 ZYNQMP_SILICON_V4,
42};
43
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +053044enum {
45 TCM_LOCK,
46 TCM_SPLIT,
47};
48
Michal Simek04b7e622015-01-15 10:01:51 +010049unsigned int zynqmp_get_silicon_version(void);
50
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +053051void initialize_tcm(bool mode);
Nitin Jain9bcc76f2018-04-20 12:30:40 +053052void mem_map_fill(void);
Siva Durga Prasad Paladugu48eaa0c2018-10-05 15:09:05 +053053#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
54void tcm_init(u8 mode);
55#endif
Siva Durga Prasad Paladugucd35d522017-07-25 11:51:38 +053056
Michal Simek04b7e622015-01-15 10:01:51 +010057#endif /* _ASM_ARCH_SYS_PROTO_H */