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Ilya Yanoke93a4a52009-07-21 19:32:21 +04001/*
2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Ilya Yanoke93a4a52009-07-21 19:32:21 +04009 */
10
11#include <common.h>
Jagan Teki484f0212016-12-06 00:00:49 +010012#include <dm.h>
Ilya Yanoke93a4a52009-07-21 19:32:21 +040013#include <malloc.h>
Simon Glass2dd337a2015-09-02 17:24:58 -060014#include <memalign.h>
Jagan Tekic6cd8d52016-12-06 00:00:50 +010015#include <miiphy.h>
Ilya Yanoke93a4a52009-07-21 19:32:21 +040016#include <net.h>
Jeroen Hofstee120f43f2014-10-08 22:57:40 +020017#include <netdev.h>
Ilya Yanoke93a4a52009-07-21 19:32:21 +040018#include "fec_mxc.h"
19
Ilya Yanoke93a4a52009-07-21 19:32:21 +040020#include <asm/io.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090021#include <linux/errno.h>
Marek Vasut4d85b032012-08-26 10:19:20 +000022#include <linux/compiler.h>
Ilya Yanoke93a4a52009-07-21 19:32:21 +040023
Jagan Tekic6cd8d52016-12-06 00:00:50 +010024#include <asm/arch/clock.h>
25#include <asm/arch/imx-regs.h>
26#include <asm/imx-common/sys_proto.h>
27
Ilya Yanoke93a4a52009-07-21 19:32:21 +040028DECLARE_GLOBAL_DATA_PTR;
29
Marek Vasut5f1631d2012-08-29 03:49:49 +000030/*
31 * Timeout the transfer after 5 mS. This is usually a bit more, since
32 * the code in the tightloops this timeout is used in adds some overhead.
33 */
34#define FEC_XFER_TIMEOUT 5000
35
Fabio Estevam8b798b22014-08-25 13:34:16 -030036/*
37 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
38 * 64-byte alignment in the DMA RX FEC buffer.
39 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
40 * satisfies the alignment on other SoCs (32-bytes)
41 */
42#define FEC_DMA_RX_MINALIGN 64
43
Ilya Yanoke93a4a52009-07-21 19:32:21 +040044#ifndef CONFIG_MII
45#error "CONFIG_MII has to be defined!"
46#endif
47
Eric Nelson3d2f7272012-03-15 18:33:25 +000048#ifndef CONFIG_FEC_XCV_TYPE
49#define CONFIG_FEC_XCV_TYPE MII100
Marek Vasutdbb4fce2011-09-11 18:05:33 +000050#endif
51
Marek Vasut6a5fd4c2011-11-08 23:18:10 +000052/*
53 * The i.MX28 operates with packets in big endian. We need to swap them before
54 * sending and after receiving.
55 */
Eric Nelson3d2f7272012-03-15 18:33:25 +000056#ifdef CONFIG_MX28
57#define CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasut6a5fd4c2011-11-08 23:18:10 +000058#endif
59
Eric Nelson3d2f7272012-03-15 18:33:25 +000060#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
61
62/* Check various alignment issues at compile time */
63#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
64#error "ARCH_DMA_MINALIGN must be multiple of 16!"
65#endif
66
67#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
68 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
69#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
70#endif
71
Ilya Yanoke93a4a52009-07-21 19:32:21 +040072#undef DEBUG
73
Eric Nelson3d2f7272012-03-15 18:33:25 +000074#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasut6a5fd4c2011-11-08 23:18:10 +000075static void swap_packet(uint32_t *packet, int length)
76{
77 int i;
78
79 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
80 packet[i] = __swab32(packet[i]);
81}
82#endif
83
Jagan Tekic6cd8d52016-12-06 00:00:50 +010084/* MII-interface related functions */
85static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
86 uint8_t regaddr)
Ilya Yanoke93a4a52009-07-21 19:32:21 +040087{
Ilya Yanoke93a4a52009-07-21 19:32:21 +040088 uint32_t reg; /* convenient holder for the PHY register */
89 uint32_t phy; /* convenient holder for the PHY */
90 uint32_t start;
Troy Kisky2000c662012-02-07 14:08:47 +000091 int val;
Ilya Yanoke93a4a52009-07-21 19:32:21 +040092
93 /*
94 * reading from any PHY's register is done by properly
95 * programming the FEC's MII data register.
96 */
Marek Vasutbf2386b2011-09-11 18:05:34 +000097 writel(FEC_IEVENT_MII, &eth->ievent);
Jagan Tekic6cd8d52016-12-06 00:00:50 +010098 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
99 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400100
101 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
Marek Vasutbf2386b2011-09-11 18:05:34 +0000102 phy | reg, &eth->mii_data);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400103
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100104 /* wait for the related interrupt */
Graeme Russf8b82ee2011-07-15 23:31:37 +0000105 start = get_timer(0);
Marek Vasutbf2386b2011-09-11 18:05:34 +0000106 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400107 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
108 printf("Read MDIO failed...\n");
109 return -1;
110 }
111 }
112
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100113 /* clear mii interrupt bit */
Marek Vasutbf2386b2011-09-11 18:05:34 +0000114 writel(FEC_IEVENT_MII, &eth->ievent);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400115
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100116 /* it's now safe to read the PHY's register */
Troy Kisky2000c662012-02-07 14:08:47 +0000117 val = (unsigned short)readl(&eth->mii_data);
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100118 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
119 regaddr, val);
Troy Kisky2000c662012-02-07 14:08:47 +0000120 return val;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400121}
122
Troy Kisky5e762652012-10-22 16:40:41 +0000123static void fec_mii_setspeed(struct ethernet_regs *eth)
Stefano Babic889f2e22010-02-01 14:51:30 +0100124{
125 /*
126 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
127 * and do not drop the Preamble.
Måns Rullgård4aeddb72015-12-08 15:38:45 +0000128 *
129 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
130 * MII_SPEED) register that defines the MDIO output hold time. Earlier
131 * versions are RAZ there, so just ignore the difference and write the
132 * register always.
133 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
134 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
135 * output.
136 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
137 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
138 * holdtime cannot result in a value greater than 3.
Stefano Babic889f2e22010-02-01 14:51:30 +0100139 */
Måns Rullgård4aeddb72015-12-08 15:38:45 +0000140 u32 pclk = imx_get_fecclk();
141 u32 speed = DIV_ROUND_UP(pclk, 5000000);
142 u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
Markus Niebel1af82742014-02-05 10:54:11 +0100143#ifdef FEC_QUIRK_ENET_MAC
144 speed--;
145#endif
Måns Rullgård4aeddb72015-12-08 15:38:45 +0000146 writel(speed << 1 | hold << 8, &eth->mii_speed);
Troy Kisky5e762652012-10-22 16:40:41 +0000147 debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
Stefano Babic889f2e22010-02-01 14:51:30 +0100148}
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400149
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100150static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
151 uint8_t regaddr, uint16_t data)
Troy Kisky2000c662012-02-07 14:08:47 +0000152{
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400153 uint32_t reg; /* convenient holder for the PHY register */
154 uint32_t phy; /* convenient holder for the PHY */
155 uint32_t start;
156
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100157 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
158 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400159
160 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
Marek Vasutbf2386b2011-09-11 18:05:34 +0000161 FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400162
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100163 /* wait for the MII interrupt */
Graeme Russf8b82ee2011-07-15 23:31:37 +0000164 start = get_timer(0);
Marek Vasutbf2386b2011-09-11 18:05:34 +0000165 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400166 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
167 printf("Write MDIO failed...\n");
168 return -1;
169 }
170 }
171
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100172 /* clear MII interrupt bit */
Marek Vasutbf2386b2011-09-11 18:05:34 +0000173 writel(FEC_IEVENT_MII, &eth->ievent);
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100174 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
175 regaddr, data);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400176
177 return 0;
178}
179
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100180static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
181 int regaddr)
Troy Kisky2000c662012-02-07 14:08:47 +0000182{
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100183 return fec_mdio_read(bus->priv, phyaddr, regaddr);
Troy Kisky2000c662012-02-07 14:08:47 +0000184}
185
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100186static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
187 int regaddr, u16 data)
Troy Kisky2000c662012-02-07 14:08:47 +0000188{
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100189 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
Troy Kisky2000c662012-02-07 14:08:47 +0000190}
191
192#ifndef CONFIG_PHYLIB
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400193static int miiphy_restart_aneg(struct eth_device *dev)
194{
Stefano Babicd6228172012-02-22 00:24:35 +0000195 int ret = 0;
196#if !defined(CONFIG_FEC_MXC_NO_ANEG)
Marek Vasutedcd6c02011-09-16 01:13:47 +0200197 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky2000c662012-02-07 14:08:47 +0000198 struct ethernet_regs *eth = fec->bus->priv;
Marek Vasutedcd6c02011-09-16 01:13:47 +0200199
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400200 /*
201 * Wake up from sleep if necessary
202 * Reset PHY, then delay 300ns
203 */
John Rigbye650e492010-01-25 23:12:55 -0700204#ifdef CONFIG_MX27
Troy Kisky2000c662012-02-07 14:08:47 +0000205 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
John Rigbye650e492010-01-25 23:12:55 -0700206#endif
Troy Kisky2000c662012-02-07 14:08:47 +0000207 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400208 udelay(1000);
209
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100210 /* Set the auto-negotiation advertisement register bits */
Troy Kisky2000c662012-02-07 14:08:47 +0000211 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100212 LPA_100FULL | LPA_100HALF | LPA_10FULL |
213 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
Troy Kisky2000c662012-02-07 14:08:47 +0000214 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100215 BMCR_ANENABLE | BMCR_ANRESTART);
Marek Vasut539ecee2011-09-11 18:05:36 +0000216
217 if (fec->mii_postcall)
218 ret = fec->mii_postcall(fec->phy_id);
219
Stefano Babicd6228172012-02-22 00:24:35 +0000220#endif
Marek Vasut539ecee2011-09-11 18:05:36 +0000221 return ret;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400222}
223
Hannes Schmelzer5a15c1a2016-06-22 12:07:14 +0200224#ifndef CONFIG_FEC_FIXED_SPEED
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400225static int miiphy_wait_aneg(struct eth_device *dev)
226{
227 uint32_t start;
Troy Kisky2000c662012-02-07 14:08:47 +0000228 int status;
Marek Vasutedcd6c02011-09-16 01:13:47 +0200229 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky2000c662012-02-07 14:08:47 +0000230 struct ethernet_regs *eth = fec->bus->priv;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400231
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100232 /* Wait for AN completion */
Graeme Russf8b82ee2011-07-15 23:31:37 +0000233 start = get_timer(0);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400234 do {
235 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
236 printf("%s: Autonegotiation timeout\n", dev->name);
237 return -1;
238 }
239
Troy Kisky2000c662012-02-07 14:08:47 +0000240 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
241 if (status < 0) {
242 printf("%s: Autonegotiation failed. status: %d\n",
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100243 dev->name, status);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400244 return -1;
245 }
Mike Frysingerd63ee712010-12-23 15:40:12 -0500246 } while (!(status & BMSR_LSTATUS));
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400247
248 return 0;
249}
Hannes Schmelzer5a15c1a2016-06-22 12:07:14 +0200250#endif /* CONFIG_FEC_FIXED_SPEED */
Troy Kisky2000c662012-02-07 14:08:47 +0000251#endif
252
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400253static int fec_rx_task_enable(struct fec_priv *fec)
254{
Marek Vasutc1582c02012-08-29 03:49:51 +0000255 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400256 return 0;
257}
258
259static int fec_rx_task_disable(struct fec_priv *fec)
260{
261 return 0;
262}
263
264static int fec_tx_task_enable(struct fec_priv *fec)
265{
Marek Vasutc1582c02012-08-29 03:49:51 +0000266 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400267 return 0;
268}
269
270static int fec_tx_task_disable(struct fec_priv *fec)
271{
272 return 0;
273}
274
275/**
276 * Initialize receive task's buffer descriptors
277 * @param[in] fec all we know about the device yet
278 * @param[in] count receive buffer count to be allocated
Eric Nelson3d2f7272012-03-15 18:33:25 +0000279 * @param[in] dsize desired size of each receive buffer
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400280 * @return 0 on success
281 *
Marek Vasut03880452013-10-12 20:36:25 +0200282 * Init all RX descriptors to default values.
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400283 */
Marek Vasut03880452013-10-12 20:36:25 +0200284static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400285{
Eric Nelson3d2f7272012-03-15 18:33:25 +0000286 uint32_t size;
Marek Vasut03880452013-10-12 20:36:25 +0200287 uint8_t *data;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000288 int i;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400289
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400290 /*
Marek Vasut03880452013-10-12 20:36:25 +0200291 * Reload the RX descriptors with default values and wipe
292 * the RX buffers.
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400293 */
Eric Nelson3d2f7272012-03-15 18:33:25 +0000294 size = roundup(dsize, ARCH_DMA_MINALIGN);
295 for (i = 0; i < count; i++) {
Marek Vasut03880452013-10-12 20:36:25 +0200296 data = (uint8_t *)fec->rbd_base[i].data_pointer;
297 memset(data, 0, dsize);
298 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
299
300 fec->rbd_base[i].status = FEC_RBD_EMPTY;
301 fec->rbd_base[i].data_length = 0;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000302 }
303
304 /* Mark the last RBD to close the ring. */
Marek Vasut03880452013-10-12 20:36:25 +0200305 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400306 fec->rbd_index = 0;
307
Marek Vasut03880452013-10-12 20:36:25 +0200308 flush_dcache_range((unsigned)fec->rbd_base,
309 (unsigned)fec->rbd_base + size);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400310}
311
312/**
313 * Initialize transmit task's buffer descriptors
314 * @param[in] fec all we know about the device yet
315 *
316 * Transmit buffers are created externally. We only have to init the BDs here.\n
317 * Note: There is a race condition in the hardware. When only one BD is in
318 * use it must be marked with the WRAP bit to use it for every transmitt.
319 * This bit in combination with the READY bit results into double transmit
320 * of each data buffer. It seems the state machine checks READY earlier then
321 * resetting it after the first transfer.
322 * Using two BDs solves this issue.
323 */
324static void fec_tbd_init(struct fec_priv *fec)
325{
Eric Nelson3d2f7272012-03-15 18:33:25 +0000326 unsigned addr = (unsigned)fec->tbd_base;
327 unsigned size = roundup(2 * sizeof(struct fec_bd),
328 ARCH_DMA_MINALIGN);
Marek Vasut03880452013-10-12 20:36:25 +0200329
330 memset(fec->tbd_base, 0, size);
331 fec->tbd_base[0].status = 0;
332 fec->tbd_base[1].status = FEC_TBD_WRAP;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400333 fec->tbd_index = 0;
Marek Vasut03880452013-10-12 20:36:25 +0200334 flush_dcache_range(addr, addr + size);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400335}
336
337/**
338 * Mark the given read buffer descriptor as free
339 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100340 * @param[in] prbd buffer descriptor to mark free again
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400341 */
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100342static void fec_rbd_clean(int last, struct fec_bd *prbd)
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400343{
Eric Nelson3d2f7272012-03-15 18:33:25 +0000344 unsigned short flags = FEC_RBD_EMPTY;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400345 if (last)
Eric Nelson3d2f7272012-03-15 18:33:25 +0000346 flags |= FEC_RBD_WRAP;
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100347 writew(flags, &prbd->status);
348 writew(0, &prbd->data_length);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400349}
350
Jagan Tekibc5fb462016-12-06 00:00:48 +0100351static int fec_get_hwaddr(int dev_id, unsigned char *mac)
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400352{
Fabio Estevam04fc1282011-12-20 05:46:31 +0000353 imx_get_mac_from_fuse(dev_id, mac);
Joe Hershberger8ecdbed2015-04-08 01:41:04 -0500354 return !is_valid_ethaddr(mac);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400355}
356
Jagan Teki484f0212016-12-06 00:00:49 +0100357#ifdef CONFIG_DM_ETH
358static int fecmxc_set_hwaddr(struct udevice *dev)
359#else
Stefano Babic889f2e22010-02-01 14:51:30 +0100360static int fec_set_hwaddr(struct eth_device *dev)
Jagan Teki484f0212016-12-06 00:00:49 +0100361#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400362{
Jagan Teki484f0212016-12-06 00:00:49 +0100363#ifdef CONFIG_DM_ETH
364 struct fec_priv *fec = dev_get_priv(dev);
365 struct eth_pdata *pdata = dev_get_platdata(dev);
366 uchar *mac = pdata->enetaddr;
367#else
Stefano Babic889f2e22010-02-01 14:51:30 +0100368 uchar *mac = dev->enetaddr;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400369 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki484f0212016-12-06 00:00:49 +0100370#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400371
372 writel(0, &fec->eth->iaddr1);
373 writel(0, &fec->eth->iaddr2);
374 writel(0, &fec->eth->gaddr1);
375 writel(0, &fec->eth->gaddr2);
376
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100377 /* Set physical address */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400378 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100379 &fec->eth->paddr1);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400380 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
381
382 return 0;
383}
384
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100385/* Do initial configuration of the FEC registers */
Marek Vasut335cbd22012-05-01 11:09:41 +0000386static void fec_reg_setup(struct fec_priv *fec)
387{
388 uint32_t rcntrl;
389
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100390 /* Set interrupt mask register */
Marek Vasut335cbd22012-05-01 11:09:41 +0000391 writel(0x00000000, &fec->eth->imask);
392
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100393 /* Clear FEC-Lite interrupt event register(IEVENT) */
Marek Vasut335cbd22012-05-01 11:09:41 +0000394 writel(0xffffffff, &fec->eth->ievent);
395
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100396 /* Set FEC-Lite receive control register(R_CNTRL): */
Marek Vasut335cbd22012-05-01 11:09:41 +0000397
398 /* Start with frame length = 1518, common for all modes. */
399 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
benoit.thebaudeau@advansacc7a282012-07-19 02:12:46 +0000400 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
401 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
402 if (fec->xcv_type == RGMII)
Marek Vasut335cbd22012-05-01 11:09:41 +0000403 rcntrl |= FEC_RCNTRL_RGMII;
404 else if (fec->xcv_type == RMII)
405 rcntrl |= FEC_RCNTRL_RMII;
Marek Vasut335cbd22012-05-01 11:09:41 +0000406
407 writel(rcntrl, &fec->eth->r_cntrl);
408}
409
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400410/**
411 * Start the FEC engine
412 * @param[in] dev Our device to handle
413 */
Jagan Teki484f0212016-12-06 00:00:49 +0100414#ifdef CONFIG_DM_ETH
415static int fec_open(struct udevice *dev)
416#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400417static int fec_open(struct eth_device *edev)
Jagan Teki484f0212016-12-06 00:00:49 +0100418#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400419{
Jagan Teki484f0212016-12-06 00:00:49 +0100420#ifdef CONFIG_DM_ETH
421 struct fec_priv *fec = dev_get_priv(dev);
422#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400423 struct fec_priv *fec = (struct fec_priv *)edev->priv;
Jagan Teki484f0212016-12-06 00:00:49 +0100424#endif
Troy Kisky01112132012-02-07 14:08:46 +0000425 int speed;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000426 uint32_t addr, size;
427 int i;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400428
429 debug("fec_open: fec_open(dev)\n");
430 /* full-duplex, heartbeat disabled */
431 writel(1 << 2, &fec->eth->x_cntrl);
432 fec->rbd_index = 0;
433
Eric Nelson3d2f7272012-03-15 18:33:25 +0000434 /* Invalidate all descriptors */
435 for (i = 0; i < FEC_RBD_NUM - 1; i++)
436 fec_rbd_clean(0, &fec->rbd_base[i]);
437 fec_rbd_clean(1, &fec->rbd_base[i]);
438
439 /* Flush the descriptors into RAM */
440 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
441 ARCH_DMA_MINALIGN);
442 addr = (uint32_t)fec->rbd_base;
443 flush_dcache_range(addr, addr + size);
444
Troy Kisky01112132012-02-07 14:08:46 +0000445#ifdef FEC_QUIRK_ENET_MAC
Jason Liubbcef6c2011-12-16 05:17:07 +0000446 /* Enable ENET HW endian SWAP */
447 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100448 &fec->eth->ecntrl);
Jason Liubbcef6c2011-12-16 05:17:07 +0000449 /* Enable ENET store and forward mode */
450 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100451 &fec->eth->x_wmrk);
Jason Liubbcef6c2011-12-16 05:17:07 +0000452#endif
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100453 /* Enable FEC-Lite controller */
John Rigbye650e492010-01-25 23:12:55 -0700454 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100455 &fec->eth->ecntrl);
456
Fabio Estevam84c1f522013-09-13 00:36:27 -0300457#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
John Rigby99d5fed2010-01-25 23:12:57 -0700458 udelay(100);
John Rigby99d5fed2010-01-25 23:12:57 -0700459
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100460 /* setup the MII gasket for RMII mode */
John Rigby99d5fed2010-01-25 23:12:57 -0700461 /* disable the gasket */
462 writew(0, &fec->eth->miigsk_enr);
463
464 /* wait for the gasket to be disabled */
465 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
466 udelay(2);
467
468 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
469 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
470
471 /* re-enable the gasket */
472 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
473
474 /* wait until MII gasket is ready */
475 int max_loops = 10;
476 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
477 if (--max_loops <= 0) {
478 printf("WAIT for MII Gasket ready timed out\n");
479 break;
480 }
481 }
482#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400483
Troy Kisky2000c662012-02-07 14:08:47 +0000484#ifdef CONFIG_PHYLIB
Troy Kisky2c42b3c2012-10-22 16:40:45 +0000485 {
Troy Kisky2000c662012-02-07 14:08:47 +0000486 /* Start up the PHY */
Timur Tabi42387462012-07-09 08:52:43 +0000487 int ret = phy_startup(fec->phydev);
488
489 if (ret) {
490 printf("Could not initialize PHY %s\n",
491 fec->phydev->dev->name);
492 return ret;
493 }
Troy Kisky2000c662012-02-07 14:08:47 +0000494 speed = fec->phydev->speed;
Troy Kisky2000c662012-02-07 14:08:47 +0000495 }
Hannes Schmelzer5a15c1a2016-06-22 12:07:14 +0200496#elif CONFIG_FEC_FIXED_SPEED
497 speed = CONFIG_FEC_FIXED_SPEED;
Troy Kisky2000c662012-02-07 14:08:47 +0000498#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400499 miiphy_wait_aneg(edev);
Troy Kisky01112132012-02-07 14:08:46 +0000500 speed = miiphy_speed(edev->name, fec->phy_id);
Marek Vasutedcd6c02011-09-16 01:13:47 +0200501 miiphy_duplex(edev->name, fec->phy_id);
Troy Kisky2000c662012-02-07 14:08:47 +0000502#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400503
Troy Kisky01112132012-02-07 14:08:46 +0000504#ifdef FEC_QUIRK_ENET_MAC
505 {
506 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
Alison Wang89d932a2013-05-27 22:55:43 +0000507 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
Troy Kisky01112132012-02-07 14:08:46 +0000508 if (speed == _1000BASET)
509 ecr |= FEC_ECNTRL_SPEED;
510 else if (speed != _100BASET)
511 rcr |= FEC_RCNTRL_RMII_10T;
512 writel(ecr, &fec->eth->ecntrl);
513 writel(rcr, &fec->eth->r_cntrl);
514 }
515#endif
516 debug("%s:Speed=%i\n", __func__, speed);
517
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100518 /* Enable SmartDMA receive task */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400519 fec_rx_task_enable(fec);
520
521 udelay(100000);
522 return 0;
523}
524
Jagan Teki484f0212016-12-06 00:00:49 +0100525#ifdef CONFIG_DM_ETH
526static int fecmxc_init(struct udevice *dev)
527#else
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100528static int fec_init(struct eth_device *dev, bd_t *bd)
Jagan Teki484f0212016-12-06 00:00:49 +0100529#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400530{
Jagan Teki484f0212016-12-06 00:00:49 +0100531#ifdef CONFIG_DM_ETH
532 struct fec_priv *fec = dev_get_priv(dev);
533#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400534 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki484f0212016-12-06 00:00:49 +0100535#endif
Marek Vasutedcd6c02011-09-16 01:13:47 +0200536 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
Marek Vasut03880452013-10-12 20:36:25 +0200537 int i;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400538
John Rigbya4a30552010-10-13 14:31:08 -0600539 /* Initialize MAC address */
Jagan Teki484f0212016-12-06 00:00:49 +0100540#ifdef CONFIG_DM_ETH
541 fecmxc_set_hwaddr(dev);
542#else
John Rigbya4a30552010-10-13 14:31:08 -0600543 fec_set_hwaddr(dev);
Jagan Teki484f0212016-12-06 00:00:49 +0100544#endif
John Rigbya4a30552010-10-13 14:31:08 -0600545
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100546 /* Setup transmit descriptors, there are two in total. */
Marek Vasut03880452013-10-12 20:36:25 +0200547 fec_tbd_init(fec);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400548
Marek Vasut03880452013-10-12 20:36:25 +0200549 /* Setup receive descriptors. */
550 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400551
Marek Vasut335cbd22012-05-01 11:09:41 +0000552 fec_reg_setup(fec);
Marek Vasutb8f88562011-09-11 18:05:31 +0000553
benoit.thebaudeau@advans551bb362012-07-19 02:12:58 +0000554 if (fec->xcv_type != SEVENWIRE)
Troy Kisky5e762652012-10-22 16:40:41 +0000555 fec_mii_setspeed(fec->bus->priv);
Marek Vasutb8f88562011-09-11 18:05:31 +0000556
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100557 /* Set Opcode/Pause Duration Register */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400558 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
559 writel(0x2, &fec->eth->x_wmrk);
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100560
561 /* Set multicast address filter */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400562 writel(0x00000000, &fec->eth->gaddr1);
563 writel(0x00000000, &fec->eth->gaddr2);
564
Peng Fan13433fd2015-08-12 17:46:51 +0800565 /* Do not access reserved register for i.MX6UL */
Peng Fan42c24662017-04-10 19:44:33 +0800566 if (!is_mx6ul() && !is_mx6ull()) {
Peng Fan13433fd2015-08-12 17:46:51 +0800567 /* clear MIB RAM */
568 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
569 writel(0, i);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400570
Peng Fan13433fd2015-08-12 17:46:51 +0800571 /* FIFO receive start register */
572 writel(0x520, &fec->eth->r_fstart);
573 }
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400574
575 /* size and address of each buffer */
576 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
577 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
578 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
579
Troy Kisky2000c662012-02-07 14:08:47 +0000580#ifndef CONFIG_PHYLIB
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400581 if (fec->xcv_type != SEVENWIRE)
582 miiphy_restart_aneg(dev);
Troy Kisky2000c662012-02-07 14:08:47 +0000583#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400584 fec_open(dev);
585 return 0;
586}
587
588/**
589 * Halt the FEC engine
590 * @param[in] dev Our device to handle
591 */
Jagan Teki484f0212016-12-06 00:00:49 +0100592#ifdef CONFIG_DM_ETH
593static void fecmxc_halt(struct udevice *dev)
594#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400595static void fec_halt(struct eth_device *dev)
Jagan Teki484f0212016-12-06 00:00:49 +0100596#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400597{
Jagan Teki484f0212016-12-06 00:00:49 +0100598#ifdef CONFIG_DM_ETH
599 struct fec_priv *fec = dev_get_priv(dev);
600#else
Marek Vasutedcd6c02011-09-16 01:13:47 +0200601 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki484f0212016-12-06 00:00:49 +0100602#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400603 int counter = 0xffff;
604
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100605 /* issue graceful stop command to the FEC transmitter if necessary */
John Rigbye650e492010-01-25 23:12:55 -0700606 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100607 &fec->eth->x_cntrl);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400608
609 debug("eth_halt: wait for stop regs\n");
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100610 /* wait for graceful stop to register */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400611 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
John Rigbye650e492010-01-25 23:12:55 -0700612 udelay(1);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400613
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100614 /* Disable SmartDMA tasks */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400615 fec_tx_task_disable(fec);
616 fec_rx_task_disable(fec);
617
618 /*
619 * Disable the Ethernet Controller
620 * Note: this will also reset the BD index counter!
621 */
John Rigby99d5fed2010-01-25 23:12:57 -0700622 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100623 &fec->eth->ecntrl);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400624 fec->rbd_index = 0;
625 fec->tbd_index = 0;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400626 debug("eth_halt: done\n");
627}
628
629/**
630 * Transmit one frame
631 * @param[in] dev Our ethernet device to handle
632 * @param[in] packet Pointer to the data to be transmitted
633 * @param[in] length Data count in bytes
634 * @return 0 on success
635 */
Jagan Teki484f0212016-12-06 00:00:49 +0100636#ifdef CONFIG_DM_ETH
637static int fecmxc_send(struct udevice *dev, void *packet, int length)
638#else
Joe Hershberger7c31bd12012-05-21 14:45:27 +0000639static int fec_send(struct eth_device *dev, void *packet, int length)
Jagan Teki484f0212016-12-06 00:00:49 +0100640#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400641{
642 unsigned int status;
Marek Vasut4325d242012-08-26 10:19:21 +0000643 uint32_t size, end;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000644 uint32_t addr;
Marek Vasut5f1631d2012-08-29 03:49:49 +0000645 int timeout = FEC_XFER_TIMEOUT;
646 int ret = 0;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400647
648 /*
649 * This routine transmits one frame. This routine only accepts
650 * 6-byte Ethernet addresses.
651 */
Jagan Teki484f0212016-12-06 00:00:49 +0100652#ifdef CONFIG_DM_ETH
653 struct fec_priv *fec = dev_get_priv(dev);
654#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400655 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki484f0212016-12-06 00:00:49 +0100656#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400657
658 /*
659 * Check for valid length of data.
660 */
661 if ((length > 1500) || (length <= 0)) {
Stefano Babic889f2e22010-02-01 14:51:30 +0100662 printf("Payload (%d) too large\n", length);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400663 return -1;
664 }
665
666 /*
Eric Nelson3d2f7272012-03-15 18:33:25 +0000667 * Setup the transmit buffer. We are always using the first buffer for
668 * transmission, the second will be empty and only used to stop the DMA
669 * engine. We also flush the packet to RAM here to avoid cache trouble.
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400670 */
Eric Nelson3d2f7272012-03-15 18:33:25 +0000671#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasut6a5fd4c2011-11-08 23:18:10 +0000672 swap_packet((uint32_t *)packet, length);
673#endif
Eric Nelson3d2f7272012-03-15 18:33:25 +0000674
675 addr = (uint32_t)packet;
Marek Vasut4325d242012-08-26 10:19:21 +0000676 end = roundup(addr + length, ARCH_DMA_MINALIGN);
677 addr &= ~(ARCH_DMA_MINALIGN - 1);
678 flush_dcache_range(addr, end);
Eric Nelson3d2f7272012-03-15 18:33:25 +0000679
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400680 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
Eric Nelson3d2f7272012-03-15 18:33:25 +0000681 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
682
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400683 /*
684 * update BD's status now
685 * This block:
686 * - is always the last in a chain (means no chain)
687 * - should transmitt the CRC
688 * - might be the last BD in the list, so the address counter should
689 * wrap (-> keep the WRAP flag)
690 */
691 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
692 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
693 writew(status, &fec->tbd_base[fec->tbd_index].status);
694
695 /*
Eric Nelson3d2f7272012-03-15 18:33:25 +0000696 * Flush data cache. This code flushes both TX descriptors to RAM.
697 * After this code, the descriptors will be safely in RAM and we
698 * can start DMA.
699 */
700 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
701 addr = (uint32_t)fec->tbd_base;
702 flush_dcache_range(addr, addr + size);
703
704 /*
Marek Vasutd521b3c2013-07-12 01:03:04 +0200705 * Below we read the DMA descriptor's last four bytes back from the
706 * DRAM. This is important in order to make sure that all WRITE
707 * operations on the bus that were triggered by previous cache FLUSH
708 * have completed.
709 *
710 * Otherwise, on MX28, it is possible to observe a corruption of the
711 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
712 * for the bus structure of MX28. The scenario is as follows:
713 *
714 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
715 * to DRAM due to flush_dcache_range()
716 * 2) ARM core writes the FEC registers via AHB_ARB2
717 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
718 *
719 * Note that 2) does sometimes finish before 1) due to reordering of
720 * WRITE accesses on the AHB bus, therefore triggering 3) before the
721 * DMA descriptor is fully written into DRAM. This results in occasional
722 * corruption of the DMA descriptor.
723 */
724 readl(addr + size - 4);
725
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100726 /* Enable SmartDMA transmit task */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400727 fec_tx_task_enable(fec);
728
729 /*
Eric Nelson3d2f7272012-03-15 18:33:25 +0000730 * Wait until frame is sent. On each turn of the wait cycle, we must
731 * invalidate data cache to see what's really in RAM. Also, we need
732 * barrier here.
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400733 */
Marek Vasut9bf7bf02012-08-29 03:49:50 +0000734 while (--timeout) {
Marek Vasutc1582c02012-08-29 03:49:51 +0000735 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
Marek Vasut5f1631d2012-08-29 03:49:49 +0000736 break;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400737 }
Eric Nelson3d2f7272012-03-15 18:33:25 +0000738
Fabio Estevamc34e99f2014-08-25 13:34:17 -0300739 if (!timeout) {
Marek Vasut9bf7bf02012-08-29 03:49:50 +0000740 ret = -EINVAL;
Fabio Estevamc34e99f2014-08-25 13:34:17 -0300741 goto out;
742 }
Marek Vasut9bf7bf02012-08-29 03:49:50 +0000743
Fabio Estevamc34e99f2014-08-25 13:34:17 -0300744 /*
745 * The TDAR bit is cleared when the descriptors are all out from TX
746 * but on mx6solox we noticed that the READY bit is still not cleared
747 * right after TDAR.
748 * These are two distinct signals, and in IC simulation, we found that
749 * TDAR always gets cleared prior than the READY bit of last BD becomes
750 * cleared.
751 * In mx6solox, we use a later version of FEC IP. It looks like that
752 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
753 * version.
754 *
755 * Fix this by polling the READY bit of BD after the TDAR polling,
756 * which covers the mx6solox case and does not harm the other SoCs.
757 */
758 timeout = FEC_XFER_TIMEOUT;
759 while (--timeout) {
760 invalidate_dcache_range(addr, addr + size);
761 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
762 FEC_TBD_READY))
763 break;
764 }
765
766 if (!timeout)
Marek Vasut9bf7bf02012-08-29 03:49:50 +0000767 ret = -EINVAL;
768
Fabio Estevamc34e99f2014-08-25 13:34:17 -0300769out:
Marek Vasut9bf7bf02012-08-29 03:49:50 +0000770 debug("fec_send: status 0x%x index %d ret %i\n",
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100771 readw(&fec->tbd_base[fec->tbd_index].status),
772 fec->tbd_index, ret);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400773 /* for next transmission use the other buffer */
774 if (fec->tbd_index)
775 fec->tbd_index = 0;
776 else
777 fec->tbd_index = 1;
778
Marek Vasut5f1631d2012-08-29 03:49:49 +0000779 return ret;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400780}
781
782/**
783 * Pull one frame from the card
784 * @param[in] dev Our ethernet device to handle
785 * @return Length of packet read
786 */
Jagan Teki484f0212016-12-06 00:00:49 +0100787#ifdef CONFIG_DM_ETH
788static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
789#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400790static int fec_recv(struct eth_device *dev)
Jagan Teki484f0212016-12-06 00:00:49 +0100791#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400792{
Jagan Teki484f0212016-12-06 00:00:49 +0100793#ifdef CONFIG_DM_ETH
794 struct fec_priv *fec = dev_get_priv(dev);
795#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400796 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki484f0212016-12-06 00:00:49 +0100797#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400798 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
799 unsigned long ievent;
800 int frame_length, len = 0;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400801 uint16_t bd_status;
Marek Vasut4325d242012-08-26 10:19:21 +0000802 uint32_t addr, size, end;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000803 int i;
Fabio Estevamcc956082013-09-17 23:13:10 -0300804 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400805
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100806 /* Check if any critical events have happened */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400807 ievent = readl(&fec->eth->ievent);
808 writel(ievent, &fec->eth->ievent);
Marek Vasut478e2d02011-10-24 23:40:03 +0000809 debug("fec_recv: ievent 0x%lx\n", ievent);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400810 if (ievent & FEC_IEVENT_BABR) {
Jagan Teki484f0212016-12-06 00:00:49 +0100811#ifdef CONFIG_DM_ETH
812 fecmxc_halt(dev);
813 fecmxc_init(dev);
814#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400815 fec_halt(dev);
816 fec_init(dev, fec->bd);
Jagan Teki484f0212016-12-06 00:00:49 +0100817#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400818 printf("some error: 0x%08lx\n", ievent);
819 return 0;
820 }
821 if (ievent & FEC_IEVENT_HBERR) {
822 /* Heartbeat error */
823 writel(0x00000001 | readl(&fec->eth->x_cntrl),
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100824 &fec->eth->x_cntrl);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400825 }
826 if (ievent & FEC_IEVENT_GRA) {
827 /* Graceful stop complete */
828 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
Jagan Teki484f0212016-12-06 00:00:49 +0100829#ifdef CONFIG_DM_ETH
830 fecmxc_halt(dev);
831#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400832 fec_halt(dev);
Jagan Teki484f0212016-12-06 00:00:49 +0100833#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400834 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100835 &fec->eth->x_cntrl);
Jagan Teki484f0212016-12-06 00:00:49 +0100836#ifdef CONFIG_DM_ETH
837 fecmxc_init(dev);
838#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400839 fec_init(dev, fec->bd);
Jagan Teki484f0212016-12-06 00:00:49 +0100840#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400841 }
842 }
843
844 /*
Eric Nelson3d2f7272012-03-15 18:33:25 +0000845 * Read the buffer status. Before the status can be read, the data cache
846 * must be invalidated, because the data in RAM might have been changed
847 * by DMA. The descriptors are properly aligned to cachelines so there's
848 * no need to worry they'd overlap.
849 *
850 * WARNING: By invalidating the descriptor here, we also invalidate
851 * the descriptors surrounding this one. Therefore we can NOT change the
852 * contents of this descriptor nor the surrounding ones. The problem is
853 * that in order to mark the descriptor as processed, we need to change
854 * the descriptor. The solution is to mark the whole cache line when all
855 * descriptors in the cache line are processed.
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400856 */
Eric Nelson3d2f7272012-03-15 18:33:25 +0000857 addr = (uint32_t)rbd;
858 addr &= ~(ARCH_DMA_MINALIGN - 1);
859 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
860 invalidate_dcache_range(addr, addr + size);
861
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400862 bd_status = readw(&rbd->status);
863 debug("fec_recv: status 0x%x\n", bd_status);
864
865 if (!(bd_status & FEC_RBD_EMPTY)) {
866 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100867 ((readw(&rbd->data_length) - 4) > 14)) {
868 /* Get buffer address and size */
Albert ARIBAUD \(3ADEV\)13420302015-06-19 14:18:27 +0200869 addr = readl(&rbd->data_pointer);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400870 frame_length = readw(&rbd->data_length) - 4;
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100871 /* Invalidate data cache over the buffer */
Marek Vasut4325d242012-08-26 10:19:21 +0000872 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
873 addr &= ~(ARCH_DMA_MINALIGN - 1);
874 invalidate_dcache_range(addr, end);
Eric Nelson3d2f7272012-03-15 18:33:25 +0000875
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100876 /* Fill the buffer and pass it to upper layers */
Eric Nelson3d2f7272012-03-15 18:33:25 +0000877#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Albert ARIBAUD \(3ADEV\)13420302015-06-19 14:18:27 +0200878 swap_packet((uint32_t *)addr, frame_length);
Marek Vasut6a5fd4c2011-11-08 23:18:10 +0000879#endif
Albert ARIBAUD \(3ADEV\)13420302015-06-19 14:18:27 +0200880 memcpy(buff, (char *)addr, frame_length);
Joe Hershberger9f09a362015-04-08 01:41:06 -0500881 net_process_received_packet(buff, frame_length);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400882 len = frame_length;
883 } else {
884 if (bd_status & FEC_RBD_ERR)
Albert ARIBAUD \(3ADEV\)13420302015-06-19 14:18:27 +0200885 printf("error frame: 0x%08x 0x%08x\n",
886 addr, bd_status);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400887 }
Eric Nelson3d2f7272012-03-15 18:33:25 +0000888
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400889 /*
Eric Nelson3d2f7272012-03-15 18:33:25 +0000890 * Free the current buffer, restart the engine and move forward
891 * to the next buffer. Here we check if the whole cacheline of
892 * descriptors was already processed and if so, we mark it free
893 * as whole.
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400894 */
Eric Nelson3d2f7272012-03-15 18:33:25 +0000895 size = RXDESC_PER_CACHELINE - 1;
896 if ((fec->rbd_index & size) == size) {
897 i = fec->rbd_index - size;
898 addr = (uint32_t)&fec->rbd_base[i];
899 for (; i <= fec->rbd_index ; i++) {
900 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
901 &fec->rbd_base[i]);
902 }
903 flush_dcache_range(addr,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100904 addr + ARCH_DMA_MINALIGN);
Eric Nelson3d2f7272012-03-15 18:33:25 +0000905 }
906
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400907 fec_rx_task_enable(fec);
908 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
909 }
910 debug("fec_recv: stop\n");
911
912 return len;
913}
914
Troy Kisky4c2ddec2012-10-22 16:40:44 +0000915static void fec_set_dev_name(char *dest, int dev_id)
916{
917 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
918}
919
Marek Vasut03880452013-10-12 20:36:25 +0200920static int fec_alloc_descs(struct fec_priv *fec)
921{
922 unsigned int size;
923 int i;
924 uint8_t *data;
925
926 /* Allocate TX descriptors. */
927 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
928 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
929 if (!fec->tbd_base)
930 goto err_tx;
931
932 /* Allocate RX descriptors. */
933 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
934 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
935 if (!fec->rbd_base)
936 goto err_rx;
937
938 memset(fec->rbd_base, 0, size);
939
940 /* Allocate RX buffers. */
941
942 /* Maximum RX buffer size. */
Fabio Estevam8b798b22014-08-25 13:34:16 -0300943 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
Marek Vasut03880452013-10-12 20:36:25 +0200944 for (i = 0; i < FEC_RBD_NUM; i++) {
Fabio Estevam8b798b22014-08-25 13:34:16 -0300945 data = memalign(FEC_DMA_RX_MINALIGN, size);
Marek Vasut03880452013-10-12 20:36:25 +0200946 if (!data) {
947 printf("%s: error allocating rxbuf %d\n", __func__, i);
948 goto err_ring;
949 }
950
951 memset(data, 0, size);
952
953 fec->rbd_base[i].data_pointer = (uint32_t)data;
954 fec->rbd_base[i].status = FEC_RBD_EMPTY;
955 fec->rbd_base[i].data_length = 0;
956 /* Flush the buffer to memory. */
957 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
958 }
959
960 /* Mark the last RBD to close the ring. */
961 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
962
963 fec->rbd_index = 0;
964 fec->tbd_index = 0;
965
966 return 0;
967
968err_ring:
969 for (; i >= 0; i--)
970 free((void *)fec->rbd_base[i].data_pointer);
971 free(fec->rbd_base);
972err_rx:
973 free(fec->tbd_base);
974err_tx:
975 return -ENOMEM;
976}
977
978static void fec_free_descs(struct fec_priv *fec)
979{
980 int i;
981
982 for (i = 0; i < FEC_RBD_NUM; i++)
983 free((void *)fec->rbd_base[i].data_pointer);
984 free(fec->rbd_base);
985 free(fec->tbd_base);
986}
987
Jagan Teki484f0212016-12-06 00:00:49 +0100988struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
989{
990 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
991 struct mii_dev *bus;
992 int ret;
993
994 bus = mdio_alloc();
995 if (!bus) {
996 printf("mdio_alloc failed\n");
997 return NULL;
998 }
999 bus->read = fec_phy_read;
1000 bus->write = fec_phy_write;
1001 bus->priv = eth;
1002 fec_set_dev_name(bus->name, dev_id);
1003
1004 ret = mdio_register(bus);
1005 if (ret) {
1006 printf("mdio_register failed\n");
1007 free(bus);
1008 return NULL;
1009 }
1010 fec_mii_setspeed(eth);
1011 return bus;
1012}
1013
1014#ifndef CONFIG_DM_ETH
Troy Kiskydce4def2012-10-22 16:40:46 +00001015#ifdef CONFIG_PHYLIB
1016int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1017 struct mii_dev *bus, struct phy_device *phydev)
1018#else
1019static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1020 struct mii_dev *bus, int phy_id)
1021#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001022{
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001023 struct eth_device *edev;
Marek Vasutedcd6c02011-09-16 01:13:47 +02001024 struct fec_priv *fec;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001025 unsigned char ethaddr[6];
Andy Duan8f8e4582017-04-10 19:44:35 +08001026 char mac[16];
Marek Vasut43b10302011-09-11 18:05:37 +00001027 uint32_t start;
1028 int ret = 0;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001029
1030 /* create and fill edev struct */
1031 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1032 if (!edev) {
Marek Vasutedcd6c02011-09-16 01:13:47 +02001033 puts("fec_mxc: not enough malloc memory for eth_device\n");
Marek Vasut43b10302011-09-11 18:05:37 +00001034 ret = -ENOMEM;
1035 goto err1;
Marek Vasutedcd6c02011-09-16 01:13:47 +02001036 }
1037
1038 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1039 if (!fec) {
1040 puts("fec_mxc: not enough malloc memory for fec_priv\n");
Marek Vasut43b10302011-09-11 18:05:37 +00001041 ret = -ENOMEM;
1042 goto err2;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001043 }
Marek Vasutedcd6c02011-09-16 01:13:47 +02001044
Nobuhiro Iwamatsu1843c5b2010-10-19 14:03:42 +09001045 memset(edev, 0, sizeof(*edev));
Marek Vasutedcd6c02011-09-16 01:13:47 +02001046 memset(fec, 0, sizeof(*fec));
1047
Marek Vasut03880452013-10-12 20:36:25 +02001048 ret = fec_alloc_descs(fec);
1049 if (ret)
1050 goto err3;
1051
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001052 edev->priv = fec;
1053 edev->init = fec_init;
1054 edev->send = fec_send;
1055 edev->recv = fec_recv;
1056 edev->halt = fec_halt;
Heiko Schocher9ada5e62010-04-27 07:43:52 +02001057 edev->write_hwaddr = fec_set_hwaddr;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001058
Marek Vasutedcd6c02011-09-16 01:13:47 +02001059 fec->eth = (struct ethernet_regs *)base_addr;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001060 fec->bd = bd;
1061
Marek Vasutdbb4fce2011-09-11 18:05:33 +00001062 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001063
1064 /* Reset chip. */
John Rigbye650e492010-01-25 23:12:55 -07001065 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
Marek Vasut43b10302011-09-11 18:05:37 +00001066 start = get_timer(0);
1067 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1068 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
Vagrant Cascadian259b1fb2016-10-23 20:45:19 -07001069 printf("FEC MXC: Timeout resetting chip\n");
Marek Vasut03880452013-10-12 20:36:25 +02001070 goto err4;
Marek Vasut43b10302011-09-11 18:05:37 +00001071 }
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001072 udelay(10);
Marek Vasut43b10302011-09-11 18:05:37 +00001073 }
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001074
Marek Vasut335cbd22012-05-01 11:09:41 +00001075 fec_reg_setup(fec);
Troy Kisky4c2ddec2012-10-22 16:40:44 +00001076 fec_set_dev_name(edev->name, dev_id);
1077 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
Troy Kiskydce4def2012-10-22 16:40:46 +00001078 fec->bus = bus;
1079 fec_mii_setspeed(bus->priv);
1080#ifdef CONFIG_PHYLIB
1081 fec->phydev = phydev;
1082 phy_connect_dev(phydev, edev);
1083 /* Configure phy */
1084 phy_config(phydev);
1085#else
Marek Vasutedcd6c02011-09-16 01:13:47 +02001086 fec->phy_id = phy_id;
Troy Kiskydce4def2012-10-22 16:40:46 +00001087#endif
1088 eth_register(edev);
Andy Duan8f8e4582017-04-10 19:44:35 +08001089 /* only support one eth device, the index number pointed by dev_id */
1090 edev->index = fec->dev_id;
Troy Kiskydce4def2012-10-22 16:40:46 +00001091
Andy Duan0eaaf832017-04-10 19:44:34 +08001092 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1093 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
Troy Kiskydce4def2012-10-22 16:40:46 +00001094 memcpy(edev->enetaddr, ethaddr, 6);
Andy Duan8f8e4582017-04-10 19:44:35 +08001095 if (fec->dev_id)
1096 sprintf(mac, "eth%daddr", fec->dev_id);
1097 else
1098 strcpy(mac, "ethaddr");
1099 if (!getenv(mac))
1100 eth_setenv_enetaddr(mac, ethaddr);
Troy Kiskydce4def2012-10-22 16:40:46 +00001101 }
1102 return ret;
Marek Vasut03880452013-10-12 20:36:25 +02001103err4:
1104 fec_free_descs(fec);
Troy Kiskydce4def2012-10-22 16:40:46 +00001105err3:
1106 free(fec);
1107err2:
1108 free(edev);
1109err1:
1110 return ret;
1111}
1112
Troy Kiskydce4def2012-10-22 16:40:46 +00001113int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1114{
1115 uint32_t base_mii;
1116 struct mii_dev *bus = NULL;
1117#ifdef CONFIG_PHYLIB
1118 struct phy_device *phydev = NULL;
1119#endif
1120 int ret;
1121
Eric Nelson3d2f7272012-03-15 18:33:25 +00001122#ifdef CONFIG_MX28
Troy Kisky2000c662012-02-07 14:08:47 +00001123 /*
1124 * The i.MX28 has two ethernet interfaces, but they are not equal.
1125 * Only the first one can access the MDIO bus.
1126 */
Troy Kiskydce4def2012-10-22 16:40:46 +00001127 base_mii = MXS_ENET0_BASE;
Troy Kisky2000c662012-02-07 14:08:47 +00001128#else
Troy Kiskydce4def2012-10-22 16:40:46 +00001129 base_mii = addr;
Troy Kisky2000c662012-02-07 14:08:47 +00001130#endif
Troy Kiskydce4def2012-10-22 16:40:46 +00001131 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1132 bus = fec_get_miibus(base_mii, dev_id);
1133 if (!bus)
1134 return -ENOMEM;
Troy Kisky2c42b3c2012-10-22 16:40:45 +00001135#ifdef CONFIG_PHYLIB
Troy Kiskydce4def2012-10-22 16:40:46 +00001136 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
Troy Kisky2c42b3c2012-10-22 16:40:45 +00001137 if (!phydev) {
Måns Rullgårdc6e4a862015-12-08 15:38:46 +00001138 mdio_unregister(bus);
Troy Kisky2c42b3c2012-10-22 16:40:45 +00001139 free(bus);
Troy Kiskydce4def2012-10-22 16:40:46 +00001140 return -ENOMEM;
Troy Kisky2c42b3c2012-10-22 16:40:45 +00001141 }
Troy Kiskydce4def2012-10-22 16:40:46 +00001142 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1143#else
1144 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
Troy Kisky2c42b3c2012-10-22 16:40:45 +00001145#endif
Troy Kiskydce4def2012-10-22 16:40:46 +00001146 if (ret) {
1147#ifdef CONFIG_PHYLIB
1148 free(phydev);
1149#endif
Måns Rullgårdc6e4a862015-12-08 15:38:46 +00001150 mdio_unregister(bus);
Troy Kiskydce4def2012-10-22 16:40:46 +00001151 free(bus);
1152 }
Marek Vasut43b10302011-09-11 18:05:37 +00001153 return ret;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001154}
1155
Troy Kisky4e0eae62012-10-22 16:40:42 +00001156#ifdef CONFIG_FEC_MXC_PHYADDR
1157int fecmxc_initialize(bd_t *bd)
1158{
1159 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1160 IMX_FEC_BASE);
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001161}
Troy Kisky4e0eae62012-10-22 16:40:42 +00001162#endif
Marek Vasut539ecee2011-09-11 18:05:36 +00001163
Troy Kisky2000c662012-02-07 14:08:47 +00001164#ifndef CONFIG_PHYLIB
Marek Vasut539ecee2011-09-11 18:05:36 +00001165int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1166{
1167 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1168 fec->mii_postcall = cb;
1169 return 0;
Jagan Teki484f0212016-12-06 00:00:49 +01001170}
1171#endif
1172
1173#else
1174
Jagan Teki87e7f352016-12-06 00:00:51 +01001175static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1176{
1177 struct fec_priv *priv = dev_get_priv(dev);
1178 struct eth_pdata *pdata = dev_get_platdata(dev);
1179
1180 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1181}
1182
Jagan Teki484f0212016-12-06 00:00:49 +01001183static const struct eth_ops fecmxc_ops = {
1184 .start = fecmxc_init,
1185 .send = fecmxc_send,
1186 .recv = fecmxc_recv,
1187 .stop = fecmxc_halt,
1188 .write_hwaddr = fecmxc_set_hwaddr,
Jagan Teki87e7f352016-12-06 00:00:51 +01001189 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
Jagan Teki484f0212016-12-06 00:00:49 +01001190};
1191
1192static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1193{
1194 struct phy_device *phydev;
1195 int mask = 0xffffffff;
1196
1197#ifdef CONFIG_PHYLIB
1198 mask = 1 << CONFIG_FEC_MXC_PHYADDR;
1199#endif
1200
1201 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
1202 if (!phydev)
1203 return -ENODEV;
1204
1205 phy_connect_dev(phydev, dev);
1206
1207 priv->phydev = phydev;
1208 phy_config(phydev);
1209
1210 return 0;
1211}
1212
1213static int fecmxc_probe(struct udevice *dev)
1214{
1215 struct eth_pdata *pdata = dev_get_platdata(dev);
1216 struct fec_priv *priv = dev_get_priv(dev);
1217 struct mii_dev *bus = NULL;
1218 int dev_id = -1;
Jagan Teki484f0212016-12-06 00:00:49 +01001219 uint32_t start;
1220 int ret;
1221
1222 ret = fec_alloc_descs(priv);
1223 if (ret)
1224 return ret;
1225
1226 bus = fec_get_miibus((uint32_t)priv->eth, dev_id);
1227 if (!bus)
1228 goto err_mii;
1229
1230 priv->bus = bus;
1231 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1232 priv->interface = pdata->phy_interface;
1233 ret = fec_phy_init(priv, dev);
1234 if (ret)
1235 goto err_phy;
1236
1237 /* Reset chip. */
Jagan Tekic6cd8d52016-12-06 00:00:50 +01001238 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1239 &priv->eth->ecntrl);
Jagan Teki484f0212016-12-06 00:00:49 +01001240 start = get_timer(0);
1241 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1242 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1243 printf("FEC MXC: Timeout reseting chip\n");
1244 goto err_timeout;
1245 }
1246 udelay(10);
1247 }
1248
1249 fec_reg_setup(priv);
Jagan Teki484f0212016-12-06 00:00:49 +01001250 priv->dev_id = (dev_id == -1) ? 0 : dev_id;
1251
Jagan Teki484f0212016-12-06 00:00:49 +01001252 return 0;
1253
1254err_timeout:
1255 free(priv->phydev);
1256err_phy:
1257 mdio_unregister(bus);
1258 free(bus);
1259err_mii:
1260 fec_free_descs(priv);
1261 return ret;
Marek Vasut539ecee2011-09-11 18:05:36 +00001262}
Jagan Teki484f0212016-12-06 00:00:49 +01001263
1264static int fecmxc_remove(struct udevice *dev)
1265{
1266 struct fec_priv *priv = dev_get_priv(dev);
1267
1268 free(priv->phydev);
1269 fec_free_descs(priv);
1270 mdio_unregister(priv->bus);
1271 mdio_free(priv->bus);
1272
1273 return 0;
1274}
1275
1276static int fecmxc_ofdata_to_platdata(struct udevice *dev)
1277{
1278 struct eth_pdata *pdata = dev_get_platdata(dev);
1279 struct fec_priv *priv = dev_get_priv(dev);
1280 const char *phy_mode;
1281
Simon Glassba1dea42017-05-17 17:18:05 -06001282 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
Jagan Teki484f0212016-12-06 00:00:49 +01001283 priv->eth = (struct ethernet_regs *)pdata->iobase;
1284
1285 pdata->phy_interface = -1;
Simon Glassdd79d6e2017-01-17 16:52:55 -07001286 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1287 NULL);
Jagan Teki484f0212016-12-06 00:00:49 +01001288 if (phy_mode)
1289 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1290 if (pdata->phy_interface == -1) {
1291 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1292 return -EINVAL;
1293 }
1294
1295 /* TODO
1296 * Need to get the reset-gpio and related properties from DT
1297 * and implemet the enet reset code on .probe call
1298 */
1299
1300 return 0;
1301}
1302
1303static const struct udevice_id fecmxc_ids[] = {
1304 { .compatible = "fsl,imx6q-fec" },
1305 { }
1306};
1307
1308U_BOOT_DRIVER(fecmxc_gem) = {
1309 .name = "fecmxc",
1310 .id = UCLASS_ETH,
1311 .of_match = fecmxc_ids,
1312 .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
1313 .probe = fecmxc_probe,
1314 .remove = fecmxc_remove,
1315 .ops = &fecmxc_ops,
1316 .priv_auto_alloc_size = sizeof(struct fec_priv),
1317 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1318};
Troy Kisky2000c662012-02-07 14:08:47 +00001319#endif