blob: 7f99d07c47fcf95ccf1ddf427d8dbf0b570548ff [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glass45be32c2014-12-10 08:55:51 -07002/*
3 * Test-related constants for sandbox
4 *
5 * Copyright (c) 2014 Google, Inc
Simon Glass45be32c2014-12-10 08:55:51 -07006 */
7
8#ifndef __ASM_TEST_H
9#define __ASM_TEST_H
10
11/* The sandbox driver always permits an I2C device with this address */
Simon Glass70778bc2015-03-05 12:25:26 -070012#define SANDBOX_I2C_TEST_ADDR 0x59
13
14#define SANDBOX_PCI_VENDOR_ID 0x1234
Simon Glass21c8f1a2019-09-25 08:56:01 -060015#define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678
Simon Glass8c501022019-12-06 21:41:54 -070016#define SANDBOX_PCI_PMC_EMUL_ID 0x5677
Simon Glass937bb472019-12-06 21:41:57 -070017#define SANDBOX_PCI_P2SB_EMUL_ID 0x5676
Simon Glass70778bc2015-03-05 12:25:26 -070018#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
19#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
Simon Glass45be32c2014-12-10 08:55:51 -070020
Bin Mengd74d3122018-08-03 01:14:53 -070021#define PCI_CAP_ID_PM_OFFSET 0x50
22#define PCI_CAP_ID_EXP_OFFSET 0x60
23#define PCI_CAP_ID_MSIX_OFFSET 0x70
Alex Margineanf1274432019-06-07 11:24:24 +030024#define PCI_CAP_ID_EA_OFFSET 0x80
Bin Mengd74d3122018-08-03 01:14:53 -070025
26#define PCI_EXT_CAP_ID_ERR_OFFSET 0x100
27#define PCI_EXT_CAP_ID_VC_OFFSET 0x200
28#define PCI_EXT_CAP_ID_DSN_OFFSET 0x300
29
Bin Mengc69ae412018-08-03 01:14:46 -070030/* Useful for PCI_VDEVICE() macro */
31#define PCI_VENDOR_ID_SANDBOX SANDBOX_PCI_VENDOR_ID
32#define SWAP_CASE_DRV_DATA 0x55aa
33
Simon Glass8cc4d822015-07-06 12:54:24 -060034#define SANDBOX_CLK_RATE 32768
35
Alex Margineanf1274432019-06-07 11:24:24 +030036/* Macros used to test PCI EA capability structure */
37#define PCI_CAP_EA_BASE_LO0 0x00100000
38#define PCI_CAP_EA_BASE_LO1 0x00110000
39#define PCI_CAP_EA_BASE_LO2 0x00120000
40#define PCI_CAP_EA_BASE_LO4 0x00140000
41#define PCI_CAP_EA_BASE_HI2 0x00020000ULL
42#define PCI_CAP_EA_BASE_HI4 0x00040000ULL
43#define PCI_CAP_EA_SIZE_LO 0x0000ffff
44#define PCI_CAP_EA_SIZE_HI 0x00000010ULL
45#define PCI_EA_BAR2_MAGIC 0x72727272
46#define PCI_EA_BAR4_MAGIC 0x74747474
47
Simon Glassa847b272020-02-06 09:54:57 -070048enum {
49 SANDBOX_IRQN_PEND = 1, /* Interrupt number for 'pending' test */
50};
51
Simon Glasscd556522015-07-06 12:54:35 -060052/* System controller driver data */
53enum {
54 SYSCON0 = 32,
55 SYSCON1,
56
57 SYSCON_COUNT
58};
59
Simon Glass4c70ed92015-04-20 12:37:15 -060060/**
61 * sandbox_i2c_set_test_mode() - set test mode for running unit tests
62 *
63 * See sandbox_i2c_xfer() for the behaviour changes.
64 *
65 * @bus: sandbox I2C bus to adjust
66 * @test_mode: true to select test mode, false to run normally
67 */
68void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode);
69
Simon Glass45be32c2014-12-10 08:55:51 -070070enum sandbox_i2c_eeprom_test_mode {
71 SIE_TEST_MODE_NONE,
72 /* Permits read/write of only one byte per I2C transaction */
73 SIE_TEST_MODE_SINGLE_BYTE,
74};
75
76void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
77 enum sandbox_i2c_eeprom_test_mode mode);
78
79void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
80
Robert Beckettf695f6e2019-10-28 17:44:59 +000081void sandbox_i2c_eeprom_set_chip_addr_offset_mask(struct udevice *dev,
82 uint mask);
83
Robert Beckett1fe8a492019-10-28 17:44:58 +000084uint sanbox_i2c_eeprom_get_prev_addr(struct udevice *dev);
85
86uint sanbox_i2c_eeprom_get_prev_offset(struct udevice *dev);
87
Simon Glassc404aa62015-04-20 12:37:24 -060088/**
89 * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time
90 *
91 * @dev: RTC device to adjust
92 * @use_system_time: true to use system time, false to use @base_time
93 * @offset: RTC offset from current system/base time (-1 for no
94 * change)
95 * @return old value of RTC offset
96 */
97long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time,
98 int offset);
99
100/**
101 * sandbox_i2c_rtc_get_set_base_time() - get and set the base time
102 *
103 * @dev: RTC device to adjust
104 * @base_time: New base system time (set to -1 for no change)
105 * @return old base time
106 */
107long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time);
108
Simon Glassbe4ebd12015-11-08 23:48:06 -0700109int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str);
110
Mario Six02ad6fb2018-09-27 09:19:31 +0200111/**
112 * sandbox_osd_get_mem() - get the internal memory of a sandbox OSD
113 *
114 * @dev: OSD device for which to access the internal memory for
115 * @buf: pointer to buffer to receive the OSD memory data
116 * @buflen: length of buffer in bytes
117 */
118int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen);
Simon Glass5620cf82018-10-01 12:22:40 -0600119
120/**
121 * sandbox_pwm_get_config() - get the PWM config for a channel
122 *
123 * @dev: Device to check
124 * @channel: Channel number to check
125 * @period_ns: Period of the PWM in nanoseconds
126 * @duty_ns: Current duty cycle of the PWM in nanoseconds
127 * @enable: true if the PWM is enabled
128 * @polarity: true if the PWM polarity is active high
129 * @return 0 if OK, -ENOSPC if the PWM number is invalid
130 */
131int sandbox_pwm_get_config(struct udevice *dev, uint channel, uint *period_nsp,
132 uint *duty_nsp, bool *enablep, bool *polarityp);
133
Simon Glass36eee8c2018-11-06 15:21:41 -0700134/**
135 * sandbox_sf_set_block_protect() - Set the BP bits of the status register
136 *
137 * @dev: Device to update
138 * @bp_mask: BP bits to set (bits 2:0, so a value of 0 to 7)
139 */
140void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask);
141
Simon Glassed96cde2018-12-10 10:37:33 -0700142/**
143 * sandbox_get_codec_params() - Read back codec parameters
144 *
145 * This reads back the parameters set by audio_codec_set_params() for the
146 * sandbox audio driver. Arguments are as for that function.
147 */
148void sandbox_get_codec_params(struct udevice *dev, int *interfacep, int *ratep,
149 int *mclk_freqp, int *bits_per_samplep,
150 uint *channelsp);
151
Simon Glassc953aaf2018-12-10 10:37:34 -0700152/**
153 * sandbox_get_i2s_sum() - Read back the sum of the audio data so far
154 *
155 * This data is provided to the sandbox driver by the I2S tx_data() method.
156 *
157 * @dev: Device to check
158 * @return sum of audio data
159 */
160int sandbox_get_i2s_sum(struct udevice *dev);
161
Simon Glass76072ac2018-12-10 10:37:36 -0700162/**
163 * sandbox_get_setup_called() - Returns the number of times setup(*) was called
164 *
165 * This is used in the sound test
166 *
167 * @dev: Device to check
168 * @return call count for the setup() method
169 */
170int sandbox_get_setup_called(struct udevice *dev);
171
172/**
Simon Glass70bc14b2020-02-03 07:36:06 -0700173 * sandbox_get_sound_active() - Returns whether sound play is in progress
174 *
175 * @return true if active, false if not
176 */
177int sandbox_get_sound_active(struct udevice *dev);
178
179/**
Simon Glass76072ac2018-12-10 10:37:36 -0700180 * sandbox_get_sound_sum() - Read back the sum of the sound data so far
181 *
182 * This data is provided to the sandbox driver by the sound play() method.
183 *
184 * @dev: Device to check
185 * @return sum of audio data
186 */
187int sandbox_get_sound_sum(struct udevice *dev);
188
Simon Glass53a68b32019-02-16 20:24:50 -0700189/**
Simon Glassecd02e72019-02-16 20:24:54 -0700190 * sandbox_set_allow_beep() - Set whether the 'beep' interface is supported
191 *
192 * @dev: Device to update
193 * @allow: true to allow the start_beep() method, false to disallow it
194 */
195void sandbox_set_allow_beep(struct udevice *dev, bool allow);
196
197/**
198 * sandbox_get_beep_frequency() - Get the frequency of the current beep
199 *
200 * @dev: Device to check
201 * @return frequency of beep, if there is an active beep, else 0
202 */
203int sandbox_get_beep_frequency(struct udevice *dev);
204
205/**
Simon Glass53a68b32019-02-16 20:24:50 -0700206 * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status
207 *
208 * @dev: Device to check
209 * @return 0 if not protected, 1 if protected
210 */
211int sandbox_get_pch_spi_protect(struct udevice *dev);
212
Ramon Friedafdb3422019-04-27 11:15:24 +0300213/**
214 * sandbox_get_pci_ep_irq_count() - Get the PCI EP IRQ count
215 *
216 * @dev: Device to check
217 * @return irq count
218 */
219int sandbox_get_pci_ep_irq_count(struct udevice *dev);
220
Simon Glass72231f72019-09-25 08:56:42 -0600221/**
222 * sandbox_pci_read_bar() - Read the BAR value for a read_config operation
223 *
224 * This is used in PCI emulators to read a base address reset. This has special
225 * rules because when the register is set to 0xffffffff it can be used to
226 * discover the type and size of the BAR.
227 *
228 * @barval: Current value of the BAR
229 * @type: Type of BAR (PCI_BASE_ADDRESS_SPACE_IO or
230 * PCI_BASE_ADDRESS_MEM_TYPE_32)
231 * @size: Size of BAR in bytes
232 * @return BAR value to return from emulator
233 */
234uint sandbox_pci_read_bar(u32 barval, int type, uint size);
235
Simon Glassc667fb02019-10-11 16:16:48 -0600236/**
237 * sandbox_set_enable_memio() - Enable readl/writel() for sandbox
238 *
239 * Normally these I/O functions do nothing with sandbox. Certain tests need them
240 * to work as for other architectures, so this function can be used to enable
241 * them.
242 *
243 * @enable: true to enable, false to disable
244 */
245void sandbox_set_enable_memio(bool enable);
246
Simon Glass45be32c2014-12-10 08:55:51 -0700247#endif