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git01.mediatek.com / filogic / uboot / e6bd05e130a066e103a2c21d474f8de86afdfecc / . / arch / arm / cpu / armv7 / am33xx / clock_am43xx.c
blob: 22963b7f8530a7bc3a7b4c10b714b8b6cae61ae2 [file] [log] [blame]
Lokesh Vutla85b59362013-07-30 11:36:29 +0530[diff] [blame]1/*
2 * clock_am43xx.c
3 *
4 * clocks for AM43XX based boards
5 * Derived from AM33XX based boards
6 *
7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12#include <common.h>
13#include <asm/arch/cpu.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/hardware.h>
16#include <asm/arch/sys_proto.h>
17#include <asm/io.h>
18
19struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
20struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
Lokesh Vutla84aaa302013-12-10 15:02:17 +0530[diff] [blame]21struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
Lokesh Vutla85b59362013-07-30 11:36:29 +0530[diff] [blame]22
23const struct dpll_regs dpll_mpu_regs = {
24 .cm_clkmode_dpll = CM_WKUP + 0x560,
25 .cm_idlest_dpll = CM_WKUP + 0x564,
26 .cm_clksel_dpll = CM_WKUP + 0x56c,
27 .cm_div_m2_dpll = CM_WKUP + 0x570,
28};
29
30const struct dpll_regs dpll_core_regs = {
31 .cm_clkmode_dpll = CM_WKUP + 0x520,
32 .cm_idlest_dpll = CM_WKUP + 0x524,
33 .cm_clksel_dpll = CM_WKUP + 0x52C,
34 .cm_div_m4_dpll = CM_WKUP + 0x538,
35 .cm_div_m5_dpll = CM_WKUP + 0x53C,
36 .cm_div_m6_dpll = CM_WKUP + 0x540,
37};
38
39const struct dpll_regs dpll_per_regs = {
40 .cm_clkmode_dpll = CM_WKUP + 0x5E0,
41 .cm_idlest_dpll = CM_WKUP + 0x5E4,
42 .cm_clksel_dpll = CM_WKUP + 0x5EC,
43 .cm_div_m2_dpll = CM_WKUP + 0x5F0,
44};
45
46const struct dpll_regs dpll_ddr_regs = {
47 .cm_clkmode_dpll = CM_WKUP + 0x5A0,
48 .cm_idlest_dpll = CM_WKUP + 0x5A4,
49 .cm_clksel_dpll = CM_WKUP + 0x5AC,
50 .cm_div_m2_dpll = CM_WKUP + 0x5B0,
51};
52
53const struct dpll_params dpll_mpu = {
54 -1, -1, -1, -1, -1, -1, -1};
55const struct dpll_params dpll_core = {
56 -1, -1, -1, -1, -1, -1, -1};
57const struct dpll_params dpll_per = {
58 -1, -1, -1, -1, -1, -1, -1};
59
60void setup_clocks_for_console(void)
61{
62 /* Do not add any spl_debug prints in this function */
63 clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
64 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
65 CD_CLKCTRL_CLKTRCTRL_SHIFT);
66
67 /* Enable UART0 */
68 clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
69 MODULE_CLKCTRL_MODULEMODE_MASK,
70 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
71 MODULE_CLKCTRL_MODULEMODE_SHIFT);
72}
73
74void enable_basic_clocks(void)
75{
76 u32 *const clk_domains[] = {
77 &cmper->l3clkstctrl,
78 &cmper->l3sclkstctrl,
79 &cmper->l4lsclkstctrl,
80 &cmwkup->wkclkstctrl,
81 &cmper->emifclkstctrl,
82 0
83 };
84
85 u32 *const clk_modules_explicit_en[] = {
86 &cmper->l3clkctrl,
87 &cmper->l4lsclkctrl,
88 &cmper->l4fwclkctrl,
89 &cmwkup->wkl4wkclkctrl,
90 &cmper->l3instrclkctrl,
91 &cmper->l4hsclkctrl,
92 &cmwkup->wkgpio0clkctrl,
93 &cmwkup->wkctrlclkctrl,
94 &cmper->timer2clkctrl,
95 &cmper->gpmcclkctrl,
96 &cmper->elmclkctrl,
97 &cmper->mmc0clkctrl,
98 &cmper->mmc1clkctrl,
99 &cmwkup->wkup_i2c0ctrl,
100 &cmper->gpio1clkctrl,
101 &cmper->gpio2clkctrl,
102 &cmper->gpio3clkctrl,
103 &cmper->i2c1clkctrl,
104 &cmper->emiffwclkctrl,
105 &cmper->emifclkctrl,
106 &cmper->otfaemifclkctrl,
107 0
108 };
109
110 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
Lokesh Vutla84aaa302013-12-10 15:02:17 +0530[diff] [blame]111
112 /* Select the Master osc clk as Timer2 clock source */
113 writel(0x1, &cmdpll->clktimer2clk);
Lokesh Vutla85b59362013-07-30 11:36:29 +0530[diff] [blame]114}