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git01.mediatek.com / filogic / uboot / 4278557aa5248d9b1cc3f4efe00f52d931c3aefa / . / arch / arm / dts / k3-am625-sk-u-boot.dtsi
blob: c1685bc9ca39faeabb3428a6ce21a354ce74f2b1 [file] [log] [blame]
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Common AM625 SK dts file for SPLs
4 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
Neha Malcom Francis8f8f4fc2023-07-22 00:14:38 +0530[diff] [blame]7#include "k3-am625-sk-binman.dtsi"
8
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]9/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]12 tick-timer = &main_timer0;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]13 };
14
15 aliases {
16 mmc1 = &sdhci1;
17 };
Georgi Vlaeve9c68bf2022-06-14 17:45:31 +0300[diff] [blame]18
19 memory@80000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]20 bootph-pre-ram;
Georgi Vlaeve9c68bf2022-06-14 17:45:31 +0300[diff] [blame]21 };
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]22};
23
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]24&cbass_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]26};
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]27
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]28&main_timer0 {
29 clock-frequency = <25000000>;
30 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]31};
32
33&dmss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]35};
36
37&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]39};
40
41&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]43};
44
45&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]47};
48
49&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]51};
52
53&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]55};
56
57&wkup_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]59};
60
61&chipid {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]63};
64
65&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]67};
68
69&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]71};
72
73&main_uart0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]75};
76
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]77&cbass_mcu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]79};
80
81&cbass_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]83};
84
85&mcu_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]87};
88
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]89&sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]91};
92
93&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]94 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]95};
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]96
97&fss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]98 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]99};
100
101&ospi0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]103};
104
105&ospi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]107
108 flash@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]110
111 partitions {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]113
114 partition@3fc0000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]116 };
117 };
118 };
119};
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]120
121&cpsw3g {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]122 bootph-pre-ram;
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]123};
124
125&cpsw_port1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-pre-ram;
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]127};
128
129&cpsw_port2 {
130 status = "disabled";
131};