blob: 50171230ea8fc99d196888310d3771e9efd06815 [file] [log] [blame]
Kumar Gala2683c532011-04-13 08:37:44 -05001/*
2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala2683c532011-04-13 08:37:44 -05006 */
7
8/* MAXFRM - maximum frame length */
9#define MAXFRM_MASK 0x0000ffff
10
11#include <common.h>
12#include <phy.h>
13#include <asm/types.h>
14#include <asm/io.h>
Kumar Gala2683c532011-04-13 08:37:44 -050015#include <asm/fsl_tgec.h>
16
17#include "fm.h"
18
19#define TGEC_CMD_CFG_INIT (TGEC_CMD_CFG_NO_LEN_CHK | \
20 TGEC_CMD_CFG_RX_ER_DISC | \
21 TGEC_CMD_CFG_STAT_CLR | \
22 TGEC_CMD_CFG_PAUSE_IGNORE | \
23 TGEC_CMD_CFG_CRC_FWD)
24#define TGEC_CMD_CFG_FINAL (TGEC_CMD_CFG_NO_LEN_CHK | \
25 TGEC_CMD_CFG_RX_ER_DISC | \
26 TGEC_CMD_CFG_PAUSE_IGNORE | \
27 TGEC_CMD_CFG_CRC_FWD)
28
29static void tgec_init_mac(struct fsl_enet_mac *mac)
30{
31 struct tgec *regs = mac->base;
32
33 /* mask all interrupt */
34 out_be32(&regs->imask, IMASK_MASK_ALL);
35
36 /* clear all events */
37 out_be32(&regs->ievent, IEVENT_CLEAR_ALL);
38
39 /* set the max receive length */
40 out_be32(&regs->maxfrm, mac->max_rx_len & MAXFRM_MASK);
41
42 /*
43 * 1588 disable, insert second mac disable payload length check
44 * disable, normal operation, any rx error frame is discarded, clear
45 * counters, pause frame ignore, no promiscuous, LAN mode Rx CRC no
46 * strip, Tx CRC append, Rx disable and Tx disable
47 */
48 out_be32(&regs->command_config, TGEC_CMD_CFG_INIT);
49 udelay(1000);
50 out_be32(&regs->command_config, TGEC_CMD_CFG_FINAL);
51
52 /* multicast frame reception for the hash entry disable */
53 out_be32(&regs->hashtable_ctrl, 0);
54}
55
56static void tgec_enable_mac(struct fsl_enet_mac *mac)
57{
58 struct tgec *regs = mac->base;
59
60 setbits_be32(&regs->command_config, TGEC_CMD_CFG_RXTX_EN);
61}
62
63static void tgec_disable_mac(struct fsl_enet_mac *mac)
64{
65 struct tgec *regs = mac->base;
66
67 clrbits_be32(&regs->command_config, TGEC_CMD_CFG_RXTX_EN);
68}
69
70static void tgec_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
71{
72 struct tgec *regs = mac->base;
73 u32 mac_addr0, mac_addr1;
74
75 /*
76 * if a station address of 0x12345678ABCD, perform a write to
77 * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB
78 */
79 mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \
80 (mac_addr[1] << 8) | (mac_addr[0]);
81 out_be32(&regs->mac_addr_0, mac_addr0);
82
83 mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff;
84 out_be32(&regs->mac_addr_1, mac_addr1);
85}
86
87static void tgec_set_interface_mode(struct fsl_enet_mac *mac,
88 phy_interface_t type, int speed)
89{
90 /* nothing right now */
91 return;
92}
93
94void init_tgec(struct fsl_enet_mac *mac, void *base,
95 void *phyregs, int max_rx_len)
96{
97 mac->base = base;
98 mac->phyregs = phyregs;
99 mac->max_rx_len = max_rx_len;
100 mac->init_mac = tgec_init_mac;
101 mac->enable_mac = tgec_enable_mac;
102 mac->disable_mac = tgec_disable_mac;
103 mac->set_mac_addr = tgec_set_mac_addr;
104 mac->set_if_mode = tgec_set_interface_mode;
105}