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Tom Rini8b0c8a12018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR X11
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +08002/*
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +08004 */
5
6/dts-v1/;
7#include "rk3288-fennec.dtsi"
8
9/ {
10 model = "Rockchip RK3288 Fennec Board";
11 compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
12
13 chosen {
14 stdout-path = &uart2;
15 };
16};
17
18&dmc {
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +080019 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
20 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
21 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
22 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
23 0x8 0x1f4>;
24 rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
25 0x0 0xc3 0x6 0x2>;
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +080026 rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
27};
28
29&pinctrl {
30 u-boot,dm-pre-reloc;
31};
32
33&pwm1 {
34 status = "okay";
35};
36
37&uart2 {
38 u-boot,dm-pre-reloc;
39 reg-shift = <2>;
40};
41
42&sdmmc {
43 u-boot,dm-pre-reloc;
44};
45
46&emmc {
47 u-boot,dm-pre-reloc;
48};
49
50&gpio3 {
51 u-boot,dm-pre-reloc;
52};
53
54&gpio8 {
55 u-boot,dm-pre-reloc;
56};