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git01.mediatek.com / filogic / uboot / 5f36921b3a1da51bc1808664e3f6bb7fa58c5d5c / . / arch / arm / dts / uniphier-ph1-pro5.dtsi
blob: 6f19bf81dcef3314f377a5ba745af2eb21335d18 [file] [log] [blame]
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900[diff] [blame]1/*
2 * Device Tree Source for UniPhier PH1-Pro5 SoC
3 *
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+ X11
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "socionext,ph1-pro5";
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "socionext,uniphier-smp";
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
23 };
24
25 cpu@1 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <1>;
29 };
30 };
31
32 clocks {
33 arm_timer_clk: arm_timer_clk {
34 #clock-cells = <0>;
35 compatible = "fixed-clock";
36 clock-frequency = <50000000>;
37 };
38
39 uart_clk: uart_clk {
40 #clock-cells = <0>;
41 compatible = "fixed-clock";
42 clock-frequency = <73728000>;
43 };
44
45 i2c_clk: i2c_clk {
46 #clock-cells = <0>;
47 compatible = "fixed-clock";
48 clock-frequency = <50000000>;
49 };
50 };
51
52 soc {
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges;
57 interrupt-parent = <&intc>;
58
59 extbus: extbus {
60 compatible = "simple-bus";
61 #address-cells = <2>;
62 #size-cells = <1>;
63 };
64
65 serial0: serial@54006800 {
66 compatible = "socionext,uniphier-uart";
67 status = "disabled";
68 reg = <0x54006800 0x40>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_uart0>;
71 interrupts = <0 33 4>;
72 clocks = <&uart_clk>;
73 };
74
75 serial1: serial@54006900 {
76 compatible = "socionext,uniphier-uart";
77 status = "disabled";
78 reg = <0x54006900 0x40>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_uart1>;
81 interrupts = <0 35 4>;
82 clocks = <&uart_clk>;
83 };
84
85 serial2: serial@54006a00 {
86 compatible = "socionext,uniphier-uart";
87 status = "disabled";
88 reg = <0x54006a00 0x40>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_uart2>;
91 interrupts = <0 37 4>;
92 clocks = <&uart_clk>;
93 };
94
95 serial3: serial@54006b00 {
96 compatible = "socionext,uniphier-uart";
97 status = "disabled";
98 reg = <0x54006b00 0x40>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_uart3>;
101 interrupts = <0 177 4>;
102 clocks = <&uart_clk>;
103 };
104
105 i2c0: i2c@58780000 {
106 compatible = "socionext,uniphier-fi2c";
107 status = "disabled";
108 reg = <0x58780000 0x80>;
109 #address-cells = <1>;
110 #size-cells = <0>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_i2c0>;
113 interrupts = <0 41 4>;
114 clocks = <&i2c_clk>;
115 clock-frequency = <100000>;
116 };
117
118 i2c1: i2c@58781000 {
119 compatible = "socionext,uniphier-fi2c";
120 status = "disabled";
121 reg = <0x58781000 0x80>;
122 #address-cells = <1>;
123 #size-cells = <0>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_i2c1>;
126 interrupts = <0 42 4>;
127 clocks = <&i2c_clk>;
128 clock-frequency = <100000>;
129 };
130
131 i2c2: i2c@58782000 {
132 compatible = "socionext,uniphier-fi2c";
133 status = "disabled";
134 reg = <0x58782000 0x80>;
135 #address-cells = <1>;
136 #size-cells = <0>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_i2c2>;
139 interrupts = <0 43 4>;
140 clocks = <&i2c_clk>;
141 clock-frequency = <100000>;
142 };
143
144 i2c3: i2c@58783000 {
145 compatible = "socionext,uniphier-fi2c";
146 status = "disabled";
147 reg = <0x58783000 0x80>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_i2c3>;
152 interrupts = <0 44 4>;
153 clocks = <&i2c_clk>;
154 clock-frequency = <100000>;
155 };
156
157 /* i2c4 does not exist */
158
159 /* chip-internal connection for DMD */
160 i2c5: i2c@58785000 {
161 compatible = "socionext,uniphier-fi2c";
162 reg = <0x58785000 0x80>;
163 #address-cells = <1>;
164 #size-cells = <0>;
165 interrupts = <0 25 4>;
166 clocks = <&i2c_clk>;
167 clock-frequency = <400000>;
168 };
169
170 /* chip-internal connection for HDMI */
171 i2c6: i2c@58786000 {
172 compatible = "socionext,uniphier-fi2c";
173 reg = <0x58786000 0x80>;
174 #address-cells = <1>;
175 #size-cells = <0>;
176 interrupts = <0 26 4>;
177 clocks = <&i2c_clk>;
178 clock-frequency = <400000>;
179 };
180
181 system-bus-controller-misc@59800000 {
182 compatible = "socionext,uniphier-system-bus-controller-misc",
183 "syscon";
184 reg = <0x59800000 0x2000>;
185 };
186
187 pinctrl: pinctrl@5f801000 {
188 compatible = "socionext,ph1-pro5-pinctrl", "syscon";
189 reg = <0x5f801000 0xe00>;
190 };
191
192 timer@60000200 {
193 compatible = "arm,cortex-a9-global-timer";
194 reg = <0x60000200 0x20>;
195 interrupts = <1 11 0x304>;
196 clocks = <&arm_timer_clk>;
197 };
198
199 timer@60000600 {
200 compatible = "arm,cortex-a9-twd-timer";
201 reg = <0x60000600 0x20>;
202 interrupts = <1 13 0x304>;
203 clocks = <&arm_timer_clk>;
204 };
205
206 intc: interrupt-controller@60001000 {
207 compatible = "arm,cortex-a9-gic";
208 #interrupt-cells = <3>;
209 interrupt-controller;
210 reg = <0x60001000 0x1000>,
211 <0x60000100 0x100>;
212 };
Masahiro Yamadaa4e54cc2015-11-04 21:56:07 +0900[diff] [blame]213
214 usb0: usb@65a00000 {
215 compatible = "socionext,uniphier-xhci", "generic-xhci";
216 status = "disabled";
217 reg = <0x65a00000 0x100>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_usb0>;
220 interrupts = <0 134 4>;
221 };
222
223 usb1: usb@65c00000 {
224 compatible = "socionext,uniphier-xhci", "generic-xhci";
225 status = "disabled";
226 reg = <0x65c00000 0x100>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
229 interrupts = <0 137 4>;
230 };
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900[diff] [blame]231 };
232};
233
234/include/ "uniphier-pinctrl.dtsi"