Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 79eb29655e157fefdf13fe9cd188ef22d11579d1 / . / arch / arm / include / asm / arch-vf610 / ddrmc-vf610.h
blob: c7da2b8a5e31f7fc2c07eb45ef198b0b6ffb4f15 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]2/*
3 * Copyright (C) 2015
4 * Toradex, Inc.
5 *
6 * Authors: Stefan Agner
7 * Sanchayan Maity
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]8 */
9
10#ifndef __ASM_ARCH_VF610_DDRMC_H
11#define __ASM_ARCH_VF610_DDRMC_H
12
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]13struct ddr3_jedec_timings {
14 u8 tinit;
15 u32 trst_pwron;
16 u32 cke_inactive;
17 u8 wrlat;
18 u8 caslat_lin;
19 u8 trc;
20 u8 trrd;
21 u8 tccd;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]22 u8 tbst_int_interval;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]23 u8 tfaw;
24 u8 trp;
25 u8 twtr;
26 u8 tras_min;
27 u8 tmrd;
28 u8 trtp;
29 u32 tras_max;
30 u8 tmod;
31 u8 tckesr;
32 u8 tcke;
33 u8 trcd_int;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]34 u8 tras_lockout;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]35 u8 tdal;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]36 u8 bstlen;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]37 u16 tdll;
38 u8 trp_ab;
39 u16 tref;
40 u8 trfc;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]41 u16 tref_int;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]42 u8 tpdex;
43 u8 txpdll;
44 u8 txsnr;
45 u16 txsr;
46 u8 cksrx;
47 u8 cksre;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]48 u8 freq_chg_en;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]49 u16 zqcl;
50 u16 zqinit;
51 u8 zqcs;
52 u8 ref_per_zq;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]53 u8 zqcs_rotate;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]54 u8 aprebit;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]55 u8 cmd_age_cnt;
56 u8 age_cnt;
57 u8 q_fullness;
58 u8 odt_rd_mapcs0;
59 u8 odt_wr_mapcs0;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]60 u8 wlmrd;
61 u8 wldqsen;
62};
63
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]64struct ddrmc_cr_setting {
65 u32 setting;
66 int cr_rnum; /* CR register ; -1 for last entry */
67};
68
69struct ddrmc_phy_setting {
70 u32 setting;
71 int phy_rnum; /* PHY register ; -1 for last entry */
72};
73
74void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count);
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]75void ddrmc_phy_init(void);
76void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]77 struct ddrmc_cr_setting *board_cr_settings,
78 struct ddrmc_phy_setting *board_phy_settings,
79 int col_diff, int row_diff);
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]80
81#endif