| Fabio Estevam | 5c824dd | 2013-09-26 22:59:25 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #include <asm/arch/clock.h> |
| 10 | #include <asm/arch/imx-regs.h> |
| 11 | #include <asm/arch/iomux.h> |
| 12 | #include <asm/arch/mx6-pins.h> |
| 13 | #include <asm/errno.h> |
| 14 | #include <asm/gpio.h> |
| 15 | #include <asm/imx-common/iomux-v3.h> |
| 16 | #include <mmc.h> |
| 17 | #include <fsl_esdhc.h> |
| 18 | #include <asm/arch/crm_regs.h> |
| 19 | #include <asm/io.h> |
| 20 | #include <asm/arch/sys_proto.h> |
| 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
| 24 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 25 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| 26 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 27 | |
| 28 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
| 29 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ |
| 30 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 31 | |
| 32 | #define WDT_EN IMX_GPIO_NR(5, 4) |
| 33 | #define WDT_TRG IMX_GPIO_NR(3, 19) |
| 34 | |
| 35 | int dram_init(void) |
| 36 | { |
| 37 | gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; |
| 38 | |
| 39 | return 0; |
| 40 | } |
| 41 | |
| 42 | static iomux_v3_cfg_t const uart2_pads[] = { |
| 43 | MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 44 | MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 45 | }; |
| 46 | |
| 47 | static iomux_v3_cfg_t const usdhc3_pads[] = { |
| 48 | MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 49 | MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 50 | MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 51 | MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 52 | MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 53 | MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 54 | }; |
| 55 | |
| 56 | static iomux_v3_cfg_t const wdog_pads[] = { |
| 57 | MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 58 | MX6_PAD_EIM_D19__GPIO_3_19, |
| 59 | }; |
| 60 | |
| 61 | static void setup_iomux_uart(void) |
| 62 | { |
| 63 | imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
| 64 | } |
| 65 | |
| 66 | static void setup_iomux_wdog(void) |
| 67 | { |
| 68 | imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
| 69 | gpio_direction_output(WDT_TRG, 0); |
| 70 | gpio_direction_output(WDT_EN, 1); |
| 71 | } |
| 72 | |
| 73 | static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; |
| 74 | |
| 75 | int board_mmc_getcd(struct mmc *mmc) |
| 76 | { |
| 77 | return 1; /* Always present */ |
| 78 | } |
| 79 | |
| 80 | int board_mmc_init(bd_t *bis) |
| 81 | { |
| 82 | imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
| 83 | usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| 84 | usdhc_cfg.max_bus_width = 4; |
| 85 | |
| 86 | return fsl_esdhc_initialize(bis, &usdhc_cfg); |
| 87 | } |
| 88 | |
| 89 | int board_early_init_f(void) |
| 90 | { |
| 91 | setup_iomux_wdog(); |
| 92 | setup_iomux_uart(); |
| 93 | |
| 94 | return 0; |
| 95 | } |
| 96 | |
| 97 | int board_init(void) |
| 98 | { |
| 99 | /* address of boot parameters */ |
| 100 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | |
| 105 | int checkboard(void) |
| 106 | { |
| 107 | puts("Board: Udoo\n"); |
| 108 | |
| 109 | return 0; |
| 110 | } |