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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Peng Fane2fd36cc2016-02-03 10:06:07 +08002/*
3 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
Peng Fane2fd36cc2016-02-03 10:06:07 +08004 */
5
6#ifndef __DRIVERS_PINCTRL_IMX_H
7#define __DRIVERS_PINCTRL_IMX_H
8
9/**
10 * @base: the address to the controller in virtual memory
11 * @input_sel_base: the address of the select input in virtual memory.
12 * @flags: flags specific for each soc
Peng Fanf70bf2b2017-02-22 16:21:49 +080013 * @mux_mask: Used when SHARE_MUX_CONF_REG flag is added
Peng Fane2fd36cc2016-02-03 10:06:07 +080014 */
15struct imx_pinctrl_soc_info {
16 void __iomem *base;
17 void __iomem *input_sel_base;
18 unsigned int flags;
Peng Fanf70bf2b2017-02-22 16:21:49 +080019 unsigned int mux_mask;
Peng Fane2fd36cc2016-02-03 10:06:07 +080020};
21
22/**
23 * @dev: a pointer back to containing device
24 * @info: the soc info
25 */
26struct imx_pinctrl_priv {
27 struct udevice *dev;
28 struct imx_pinctrl_soc_info *info;
29};
30
31extern const struct pinctrl_ops imx_pinctrl_ops;
32
33#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
34#define IMX_PAD_SION 0x40000000 /* set SION */
35
36/*
37 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
38 * 1 u32 CONFIG, so 24 types in total for each pin.
39 */
40#define FSL_PIN_SIZE 24
41#define SHARE_FSL_PIN_SIZE 20
42
43#define SHARE_MUX_CONF_REG 0x1
44#define ZERO_OFFSET_VALID 0x2
Peng Fanf70bf2b2017-02-22 16:21:49 +080045#define CONFIG_IBE_OBE 0x4
Peng Fane2fd36cc2016-02-03 10:06:07 +080046
47#define IOMUXC_CONFIG_SION (0x1 << 4)
48
49int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info);
50
51int imx_pinctrl_remove(struct udevice *dev);
52#endif /* __DRIVERS_PINCTRL_IMX_H */