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git01.mediatek.com / filogic / uboot / 3a48c4d141ce760f880dfe07ef59c538cb929cb2 / . / arch / arm / dts / uniphier-ph1-ld11.dtsi
blob: 7d498cebe9cd23170280751c76dc117d06d85b04 [file] [log] [blame]
Masahiro Yamadaf0c34fc2016-03-18 16:41:49 +0900[diff] [blame]1/*
2 * Device Tree Source for UniPhier PH1-LD11 SoC
3 *
4 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+ X11
7 */
8
9/ {
10 compatible = "socionext,ph1-ld11";
11 #address-cells = <2>;
12 #size-cells = <2>;
13 interrupt-parent = <&gic>;
14
15 cpus {
16 #address-cells = <2>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a53", "arm,armv8";
22 reg = <0 0x000>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0 0x80000100>;
25 };
26
27 cpu@1 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a53", "arm,armv8";
30 reg = <0 0x001>;
31 enable-method = "spin-table";
32 cpu-release-addr = <0 0x80000100>;
33 };
34 };
35
36 clocks {
37 uart_clk: uart_clk {
38 #clock-cells = <0>;
39 compatible = "fixed-clock";
40 clock-frequency = <58820000>;
41 };
42
43 i2c_clk: i2c_clk {
44 #clock-cells = <0>;
45 compatible = "fixed-clock";
46 clock-frequency = <50000000>;
47 };
48 };
49
50 timer {
51 compatible = "arm,armv8-timer";
52 interrupts = <1 13 0xf01>,
53 <1 14 0xf01>,
54 <1 11 0xf01>,
55 <1 10 0xf01>;
56 };
57
58 soc {
59 compatible = "simple-bus";
60 #address-cells = <1>;
61 #size-cells = <1>;
62 ranges = <0 0 0 0xffffffff>;
63
64 serial0: serial@54006800 {
65 compatible = "socionext,uniphier-uart";
66 status = "disabled";
67 reg = <0x54006800 0x40>;
68 interrupts = <0 33 4>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_uart0>;
71 clocks = <&uart_clk>;
Masahiro Yamada3a48c4d2016-03-28 21:39:17 +0900[diff] [blame^]72 clock-frequency = <58820000>;
Masahiro Yamadaf0c34fc2016-03-18 16:41:49 +0900[diff] [blame]73 };
74
75 serial1: serial@54006900 {
76 compatible = "socionext,uniphier-uart";
77 status = "disabled";
78 reg = <0x54006900 0x40>;
79 interrupts = <0 35 4>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_uart1>;
82 clocks = <&uart_clk>;
Masahiro Yamada3a48c4d2016-03-28 21:39:17 +0900[diff] [blame^]83 clock-frequency = <58820000>;
Masahiro Yamadaf0c34fc2016-03-18 16:41:49 +0900[diff] [blame]84 };
85
86 serial2: serial@54006a00 {
87 compatible = "socionext,uniphier-uart";
88 status = "disabled";
89 reg = <0x54006a00 0x40>;
90 interrupts = <0 37 4>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_uart2>;
93 clocks = <&uart_clk>;
Masahiro Yamada3a48c4d2016-03-28 21:39:17 +0900[diff] [blame^]94 clock-frequency = <58820000>;
Masahiro Yamadaf0c34fc2016-03-18 16:41:49 +0900[diff] [blame]95 };
96
97 serial3: serial@54006b00 {
98 compatible = "socionext,uniphier-uart";
99 status = "disabled";
100 reg = <0x54006b00 0x40>;
101 interrupts = <0 177 4>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_uart3>;
104 clocks = <&uart_clk>;
Masahiro Yamada3a48c4d2016-03-28 21:39:17 +0900[diff] [blame^]105 clock-frequency = <58820000>;
Masahiro Yamadaf0c34fc2016-03-18 16:41:49 +0900[diff] [blame]106 };
107
108 i2c0: i2c@58780000 {
109 compatible = "socionext,uniphier-fi2c";
110 status = "disabled";
111 reg = <0x58780000 0x80>;
112 #address-cells = <1>;
113 #size-cells = <0>;
114 interrupts = <0 41 4>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_i2c0>;
117 clocks = <&i2c_clk>;
118 clock-frequency = <100000>;
119 };
120
121 i2c1: i2c@58781000 {
122 compatible = "socionext,uniphier-fi2c";
123 status = "disabled";
124 reg = <0x58781000 0x80>;
125 #address-cells = <1>;
126 #size-cells = <0>;
127 interrupts = <0 42 4>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_i2c1>;
130 clocks = <&i2c_clk>;
131 clock-frequency = <100000>;
132 };
133
134 i2c2: i2c@58782000 {
135 compatible = "socionext,uniphier-fi2c";
136 reg = <0x58782000 0x80>;
137 #address-cells = <1>;
138 #size-cells = <0>;
139 interrupts = <0 43 4>;
140 clocks = <&i2c_clk>;
141 clock-frequency = <400000>;
142 };
143
144 i2c3: i2c@58783000 {
145 compatible = "socionext,uniphier-fi2c";
146 status = "disabled";
147 reg = <0x58783000 0x80>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 interrupts = <0 44 4>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_i2c3>;
153 clocks = <&i2c_clk>;
154 clock-frequency = <100000>;
155 };
156
157 i2c4: i2c@58784000 {
158 compatible = "socionext,uniphier-fi2c";
159 status = "disabled";
160 reg = <0x58784000 0x80>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 interrupts = <0 45 4>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_i2c4>;
166 clocks = <&i2c_clk>;
167 clock-frequency = <100000>;
168 };
169
170 i2c5: i2c@58785000 {
171 compatible = "socionext,uniphier-fi2c";
172 reg = <0x58785000 0x80>;
173 #address-cells = <1>;
174 #size-cells = <0>;
175 interrupts = <0 25 4>;
176 clocks = <&i2c_clk>;
177 clock-frequency = <400000>;
178 };
179
180 system_bus: system-bus@58c00000 {
181 compatible = "socionext,uniphier-system-bus";
182 status = "disabled";
183 reg = <0x58c00000 0x400>;
184 #address-cells = <2>;
185 #size-cells = <1>;
186 };
187
188 smpctrl@59800000 {
189 compatible = "socionext,uniphier-smpctrl";
190 reg = <0x59801000 0x400>;
191 };
192
193 pinctrl: pinctrl@5f801000 {
194 compatible = "socionext,ph1-ld11-pinctrl", "syscon";
195 reg = <0x5f801000 0xe00>;
196 };
197
198 gic: interrupt-controller@5fe00000 {
199 compatible = "arm,gic-v3";
200 reg = <0x5fe00000 0x10000>, /* GICD */
201 <0x5fe40000 0x80000>; /* GICR */
202 interrupt-controller;
203 #interrupt-cells = <3>;
204 interrupts = <1 9 4>;
205 };
206 };
207};
208
209/include/ "uniphier-pinctrl.dtsi"