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git01.mediatek.com / filogic / uboot / 3a27d4b157baec15f6d3a958b38b76fe77fc9ce6 / . / arch / arm / dts / imx8mp-data-modul-edm-sbc.dts
blob: 8066f7fb649ab42cf643a781d545a6624e6dc602 [file] [log] [blame]
Marek Vasutaa2fc532023-04-04 01:07:43 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/net/qca-ar803x.h>
9#include "imx8mp.dtsi"
10
11/ {
12 model = "Data Modul i.MX8M Plus eDM SBC";
13 compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp";
14
15 aliases {
16 rtc0 = &rtc;
17 rtc1 = &snvs_rtc;
18 };
19
20 chosen {
21 stdout-path = &uart3;
22 };
23
24 memory@40000000 {
25 device_type = "memory";
26 /* There are 1/2/4 GiB options, adjusted by bootloader. */
27 reg = <0x0 0x40000000 0 0x40000000>;
28 };
29
30 backlight: backlight {
31 compatible = "pwm-backlight";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_panel_backlight>;
34 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
35 default-brightness-level = <7>;
36 enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
37 pwms = <&pwm1 0 5000000 0>;
38 /* Disabled by default, unless display board plugged in. */
39 status = "disabled";
40 };
41
42 clk_xtal25: clk-xtal25 {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <25000000>;
46 };
47
48 panel: panel {
49 backlight = <&backlight>;
50 power-supply = <&reg_panel_vcc>;
51 /* Disabled by default, unless display board plugged in. */
52 status = "disabled";
53 };
54
55 reg_panel_vcc: regulator-panel-vcc {
56 compatible = "regulator-fixed";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_panel_vcc_reg>;
59 regulator-name = "PANEL_VCC";
60 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <5000000>;
62 gpio = <&gpio3 6 0>;
63 enable-active-high;
64 /* Disabled by default, unless display board plugged in. */
65 status = "disabled";
66 };
67
68 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
69 compatible = "regulator-fixed";
70 enable-active-high;
71 gpio = <&gpio2 19 0>; /* SD2_RESET */
72 off-on-delay-us = <12000>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
75 regulator-max-microvolt = <3300000>;
76 regulator-min-microvolt = <3300000>;
77 regulator-name = "VDD_3V3_SD";
78 startup-delay-us = <100>;
79 vin-supply = <&buck4>;
80 };
81
82 watchdog {
83 /* TPS3813 */
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_watchdog_gpio>;
86 compatible = "linux,wdt-gpio";
87 always-running;
88 gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
89 hw_algo = "level";
90 /* Reset triggers in 2..3 seconds */
91 hw_margin_ms = <1500>;
92 /* Disabled by default */
93 status = "disabled";
94 };
95};
96
97&A53_0 {
98 cpu-supply = <&buck2>;
99};
100
101&A53_1 {
102 cpu-supply = <&buck2>;
103};
104
105&A53_2 {
106 cpu-supply = <&buck2>;
107};
108
109&A53_3 {
110 cpu-supply = <&buck2>;
111};
112
113&ecspi1 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_ecspi1>;
116 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
117 status = "okay";
118
119 flash@0 { /* W25Q128JVEI */
120 compatible = "jedec,spi-nor";
121 reg = <0>;
122 spi-max-frequency = <100000000>; /* Up to 133 MHz */
123 spi-tx-bus-width = <1>;
124 spi-rx-bus-width = <1>;
125 };
126};
127
128&ecspi2 { /* Feature connector SPI */
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_ecspi2>;
131 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
132 /* Disabled by default, unless feature board plugged in. */
133 status = "disabled";
134};
135
136&ecspi3 { /* Display connector SPI */
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_ecspi3>;
139 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
140 /* Disabled by default, unless display board plugged in. */
141 status = "disabled";
142};
143
144&eqos { /* First ethernet */
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_eqos>;
147 phy-handle = <&phy_eqos>;
148 phy-mode = "rgmii-id";
149 status = "okay";
150
151 mdio {
152 compatible = "snps,dwmac-mdio";
153 #address-cells = <1>;
154 #size-cells = <0>;
155
156 /* Atheros AR8031 PHY */
157 phy_eqos: ethernet-phy@0 {
158 compatible = "ethernet-phy-ieee802.3-c22";
159 reg = <0>;
160 /*
161 * Dedicated ENET_WOL# signal is unused, the PHY
162 * can wake the SoC up via INT signal as well.
163 */
164 interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
165 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
166 reset-assert-us = <10000>;
167 reset-deassert-us = <10000>;
168 qca,keep-pll-enabled;
169 vddio-supply = <&vddio_eqos>;
170
171 vddio_eqos: vddio-regulator {
172 regulator-name = "VDDIO_EQOS";
173 regulator-min-microvolt = <1800000>;
174 regulator-max-microvolt = <1800000>;
175 };
176
177 vddh_eqos: vddh-regulator {
178 regulator-name = "VDDH_EQOS";
179 };
180 };
181 };
182};
183
184&fec { /* Second ethernet */
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_fec>;
187 phy-handle = <&phy_fec>;
188 phy-mode = "rgmii-id";
189 fsl,magic-packet;
190 status = "okay";
191
192 mdio {
193 #address-cells = <1>;
194 #size-cells = <0>;
195
196 /* Atheros AR8031 PHY */
197 phy_fec: ethernet-phy@0 {
198 compatible = "ethernet-phy-ieee802.3-c22";
199 reg = <0>;
200 /*
201 * Dedicated ENET_WOL# signal is unused, the PHY
202 * can wake the SoC up via INT signal as well.
203 */
204 interrupts-extended = <&gpio2 2 IRQ_TYPE_LEVEL_LOW>;
205 reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
206 reset-assert-us = <10000>;
207 reset-deassert-us = <10000>;
208 qca,keep-pll-enabled;
209 vddio-supply = <&vddio_fec>;
210
211 vddio_fec: vddio-regulator {
212 regulator-name = "VDDIO_FEC";
213 regulator-min-microvolt = <1800000>;
214 regulator-max-microvolt = <1800000>;
215 };
216
217 vddh_fec: vddh-regulator {
218 regulator-name = "VDDH_FEC";
219 };
220 };
221 };
222};
223
224&flexcan1 {
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_flexcan1>;
227 status = "okay";
228};
229
230&gpio1 {
231 gpio-line-names =
232 "", "USBHUB_RESET#", "WDOG_B#", "PMIC_INT#",
233 "", "M2_PCIE_RST#", "M2_PCIE_WAKE#", "GPIO5_IO03",
234 "GPIO5_IO04", "PDM_SEL", "ENET_WOL#", "ENET_INT#",
235 "", "", "", "ENET_RST#",
236 "", "", "", "", "", "", "", "",
237 "", "", "", "", "", "", "", "";
238};
239
240&gpio2 {
241 gpio-line-names =
242 "", "", "ENET2_INT#", "", "", "", "", "",
243 "WDOG_KICK#", "ENET2_RST#", "CAN_INT#", "RTC_IRQ#",
244 "", "", "", "",
245 "", "", "", "SD2_RESET#", "", "", "", "",
246 "", "", "", "", "", "", "", "";
247};
248
249&gpio3 {
250 gpio-line-names =
251 "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
252 "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
253 "CSI2_PD_1V8", "CSI2_RESET_1V8#", "", "",
254 "", "", "EEPROM_WP_1V8#", "", "", "", "", "",
255 "MEMCFG0", "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#",
256 "", "M2_W_DISABLE1_1V8#",
257 "M2_W_DISABLE2_1V8#", "", "I2C5_SCL_3V3", "I2C5_SDA_3V3",
258 "", "", "", "";
259};
260
261&gpio4 {
262 gpio-line-names =
263 "DSI_RESET_1V8#", "MEMCFG2", "", "MEMCFG1", "", "", "", "",
264 "", "", "", "", "", "", "", "",
265 "", "", "GRAPHICS_PRSNT_1V8#", "DSI_IRQ_1V8#",
266 "", "DIS_USB_DN1", "DIS_USB_DN2", "",
267 "", "", "", "", "", "", "", "";
268};
269
270&gpio5 {
271 gpio-line-names =
272 "", "", "", "", "", "WDOG_EN", "", "",
273 "", "SPI1_CS#", "", "",
274 "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
275 "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
276 "", "", "", "",
277 "", "SPI3_CS#", "", "", "", "", "", "";
278};
279
280&i2c1 {
281 clock-frequency = <100000>;
282 pinctrl-names = "default", "gpio";
283 pinctrl-0 = <&pinctrl_i2c1>;
284 pinctrl-1 = <&pinctrl_i2c1_gpio>;
285 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
286 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
287 status = "okay";
288
289 usb-hub@2c {
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_usb_hub>;
292 compatible = "microchip,usb2514bi";
293 reg = <0x2c>;
294 individual-port-switching;
295 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
296 self-powered;
297 };
298
299 eeprom: eeprom@50 {
300 compatible = "atmel,24c32";
301 reg = <0x50>;
302 pagesize = <32>;
303 };
304
305 rtc: rtc@68 {
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_rtc>;
308 compatible = "st,m41t62";
309 reg = <0x68>;
310 interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
311 };
312
313 pcieclk: clk@6a {
314 compatible = "renesas,9fgv0241";
315 reg = <0x6a>;
316 clocks = <&clk_xtal25>;
317 #clock-cells = <1>;
318 };
319};
320
321&i2c2 {
322 clock-frequency = <100000>;
323 pinctrl-names = "default", "gpio";
324 pinctrl-0 = <&pinctrl_i2c2>;
325 pinctrl-1 = <&pinctrl_i2c2_gpio>;
326 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
327 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
328 status = "okay";
329};
330
331&i2c3 {
332 clock-frequency = <100000>;
333 pinctrl-names = "default", "gpio";
334 pinctrl-0 = <&pinctrl_i2c3>;
335 pinctrl-1 = <&pinctrl_i2c3_gpio>;
336 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
337 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
338 status = "okay";
339
340 pmic: pmic@25 {
341 compatible = "nxp,pca9450c";
342 reg = <0x25>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_pmic>;
345 interrupt-parent = <&gpio1>;
346 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
347 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
348
349 /*
350 * i.MX 8M Plus Data Sheet for Consumer Products
351 * 3.1.4 Operating ranges
352 * MIMX8ML8CVNKZAB
353 */
354 regulators {
355 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
356 regulator-min-microvolt = <850000>;
357 regulator-max-microvolt = <1000000>;
358 regulator-ramp-delay = <3125>;
359 regulator-always-on;
360 regulator-boot-on;
361 };
362
363 buck2: BUCK2 { /* VDD_ARM */
364 regulator-min-microvolt = <850000>;
365 regulator-max-microvolt = <1000000>;
366 regulator-ramp-delay = <3125>;
367 regulator-always-on;
368 regulator-boot-on;
369 };
370
371 buck4: BUCK4 { /* VDD_3V3 */
372 regulator-min-microvolt = <3300000>;
373 regulator-max-microvolt = <3300000>;
374 regulator-always-on;
375 regulator-boot-on;
376 };
377
378 buck5: BUCK5 { /* VDD_1V8 */
379 regulator-min-microvolt = <1800000>;
380 regulator-max-microvolt = <1800000>;
381 regulator-always-on;
382 regulator-boot-on;
383 };
384
385 buck6: BUCK6 { /* NVCC_DRAM_1V1 */
386 regulator-min-microvolt = <1100000>;
387 regulator-max-microvolt = <1100000>;
388 regulator-always-on;
389 regulator-boot-on;
390 };
391
392 ldo1: LDO1 { /* NVCC_SNVS_1V8 */
393 regulator-min-microvolt = <1800000>;
394 regulator-max-microvolt = <1800000>;
395 regulator-always-on;
396 regulator-boot-on;
397 };
398
399 ldo3: LDO3 { /* VDDA_1V8 */
400 regulator-min-microvolt = <1800000>;
401 regulator-max-microvolt = <1800000>;
402 regulator-always-on;
403 regulator-boot-on;
404 };
405
406 ldo4: LDO4 { /* PMIC_LDO4 */
407 regulator-min-microvolt = <3300000>;
408 regulator-max-microvolt = <3300000>;
409 };
410
411 ldo5: LDO5 { /* NVCC_SD2 */
412 regulator-min-microvolt = <1800000>;
413 regulator-max-microvolt = <3300000>;
414 };
415 };
416 };
417};
418
419&i2c5 { /* HDMI EDID bus */
420 clock-frequency = <100000>;
421 pinctrl-names = "default", "gpio";
422 pinctrl-0 = <&pinctrl_i2c5>;
423 pinctrl-1 = <&pinctrl_i2c5_gpio>;
424 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
425 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
426 status = "okay";
427};
428
429&iomuxc {
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
432 <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
433 <&pinctrl_panel_expansion>;
434
435 pinctrl_ecspi1: ecspi1-grp {
436 fsl,pins = <
437 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44
438 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44
439 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44
440 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40
441 >;
442 };
443
444 pinctrl_ecspi2: ecspi2-grp {
445 fsl,pins = <
446 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
447 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
448 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
449 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
450 >;
451 };
452
453 pinctrl_ecspi3: ecspi3-grp {
454 fsl,pins = <
455 MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x44
456 MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x44
457 MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x44
458 MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x40
459 >;
460 };
461
462 pinctrl_eqos: eqos-grp {
463 fsl,pins = <
464 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
465 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
466 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
467 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
468 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
469 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
470 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
471 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
472 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
473 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
474 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
475 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
476 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
477 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
478 /* ENET_RST# */
479 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6
480 /* ENET_INT# */
481 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090
482 >;
483 };
484
485 pinctrl_fec: fec-grp {
486 fsl,pins = <
487 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
488 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
489 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
490 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
491 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
492 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
493 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
494 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
495 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
496 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
497 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
498 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
499 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
500 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
501 /* ENET2_RST# */
502 MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6
503 /* ENET2_INT# */
504 MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090
505 >;
506 };
507
508 pinctrl_flexcan1: flexcan1-grp {
509 fsl,pins = <
510 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
511 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
512 >;
513 };
514
515 pinctrl_hog_feature: hog-feature-grp {
516 fsl,pins = <
517 /* GPIO5_IO03 */
518 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40000006
519 /* GPIO5_IO04 */
520 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40000006
521
522 /* CAN_INT# */
523 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x40000090
524 >;
525 };
526
527 pinctrl_hog_panel: hog-panel-grp {
528 fsl,pins = <
529 /* GRAPHICS_GPIO0_1V8 */
530 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x26
531 >;
532 };
533
534 pinctrl_hog_misc: hog-misc-grp {
535 fsl,pins = <
536 /* ENET_WOL# -- shared by both PHYs */
537 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000090
538
539 /* PG_V_IN_VAR# */
540 MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000
541 /* CSI2_PD_1V8 */
542 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0
543 /* CSI2_RESET_1V8# */
544 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0
545
546 /* DIS_USB_DN1 */
547 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0
548 /* DIS_USB_DN2 */
549 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0
550
551 /* EEPROM_WP_1V8# */
552 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x100
553 /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
554 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x0
555 /* GRAPHICS_PRSNT_1V8# */
556 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000
557
558 /* CLK_CCM_CLKO1_3V3 */
559 MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10
560 >;
561 };
562
563 pinctrl_hog_sbc: hog-sbc-grp {
564 fsl,pins = <
565 /* MEMCFG[0..2] straps */
566 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x40000140
567 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40000140
568 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000140
569 >;
570 };
571
572 pinctrl_i2c1: i2c1-grp {
573 fsl,pins = <
574 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x40000084
575 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x40000084
576 >;
577 };
578
579 pinctrl_i2c1_gpio: i2c1-gpio-grp {
580 fsl,pins = <
581 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x84
582 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x84
583 >;
584 };
585
586 pinctrl_i2c2: i2c2-grp {
587 fsl,pins = <
588 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x40000084
589 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x40000084
590 >;
591 };
592
593 pinctrl_i2c2_gpio: i2c2-gpio-grp {
594 fsl,pins = <
595 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x84
596 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x84
597 >;
598 };
599
600 pinctrl_i2c3: i2c3-grp {
601 fsl,pins = <
602 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084
603 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084
604 >;
605 };
606
607 pinctrl_i2c3_gpio: i2c3-gpio-grp {
608 fsl,pins = <
609 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84
610 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84
611 >;
612 };
613
614 pinctrl_i2c5: i2c5-grp {
615 fsl,pins = <
616 MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084
617 MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084
618 >;
619 };
620
621 pinctrl_i2c5_gpio: i2c5-gpio-grp {
622 fsl,pins = <
623 MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84
624 MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84
625 >;
626 };
627
628 pinctrl_panel_backlight: panel-backlight-grp {
629 fsl,pins = <
630 /* BL_ENABLE_1V8 */
631 MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x104
632 >;
633 };
634
635 pinctrl_panel_expansion: panel-expansion-grp {
636 fsl,pins = <
637 /* DSI_RESET_1V8# */
638 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x2
639 /* DSI_IRQ_1V8# */
640 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000090
641 >;
642 };
643
644 pinctrl_panel_pwm: panel-pwm-grp {
645 fsl,pins = <
646 /* BL_PWM_3V3 */
647 MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x12
648 >;
649 };
650
651 pinctrl_panel_vcc_reg: panel-vcc-grp {
652 fsl,pins = <
653 /* TFT_ENABLE_1V8 */
654 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x104
655 >;
656 };
657
658 pinctrl_pcie0: pcie-grp {
659 fsl,pins = <
660 /* M2_PCIE_RST# */
661 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
662 /* M2_W_DISABLE1_1V8# */
663 MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2
664 /* M2_W_DISABLE2_1V8# */
665 MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2
666 /* CLK_M2_32K768 */
667 MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14
668 /* M2_PCIE_WAKE# */
669 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140
670 /* M2_PCIE_CLKREQ# */
671 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61
672 >;
673 };
674
675 pinctrl_pdm: pdm-grp {
676 fsl,pins = <
677 /* PDM_SEL */
678 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x0
679 MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x0
680 MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x0
681 >;
682 };
683
684 pinctrl_pmic: pmic-grp {
685 fsl,pins = <
686 /* PMIC_nINT */
687 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
688 >;
689 };
690
691 pinctrl_rtc: rtc-grp {
692 fsl,pins = <
693 /* RTC_IRQ# */
694 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000090
695 >;
696 };
697
698 pinctrl_sai1: sai1-grp {
699 fsl,pins = <
700 MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0xd6
701 MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0xd6
702 MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0xd6
703 MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6
704 MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0xd6
705 >;
706 };
707
708 pinctrl_sai2: sai2-grp {
709 fsl,pins = <
710 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
711 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
712 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
713 MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
714 >;
715 };
716
717 pinctrl_sai3: sai3-grp {
718 fsl,pins = <
719 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
720 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
721 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
722 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
723 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
724 >;
725 };
726
727 pinctrl_uart1: uart1-grp {
728 fsl,pins = <
729 MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x49
730 MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x49
731 MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x49
732 MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49
733 >;
734 };
735
736 pinctrl_uart2: uart2-grp {
737 fsl,pins = <
738 MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x49
739 MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x49
740 MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49
741 MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49
742 >;
743 };
744
745 pinctrl_uart3: uart3-grp {
746 fsl,pins = <
747 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
748 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
749 >;
750 };
751
752 pinctrl_uart4: uart4-grp {
753 fsl,pins = <
754 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
755 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
756 >;
757 };
758
759 pinctrl_usdhc2: usdhc2-grp {
760 fsl,pins = <
761 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
762 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
763 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
764 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
765 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
766 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
767 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
768 >;
769 };
770
771 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
772 fsl,pins = <
773 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
774 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
775 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
776 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
777 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
778 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
779 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
780 >;
781 };
782
783 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
784 fsl,pins = <
785 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
786 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
787 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
788 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
789 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
790 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
791 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
792 >;
793 };
794
795 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
796 fsl,pins = <
797 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20
798 >;
799 };
800
801 pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
802 fsl,pins = <
803 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080
804 >;
805 };
806
807 pinctrl_usdhc3: usdhc3-grp {
808 fsl,pins = <
809 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
810 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
811 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
812 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
813 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
814 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
815 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
816 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
817 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
818 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
819 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
820 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
821 >;
822 };
823
824 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
825 fsl,pins = <
826 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
827 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
828 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
829 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
830 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
831 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
832 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
833 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
834 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
835 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
836 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
837 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
838 >;
839 };
840
841 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
842 fsl,pins = <
843 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
844 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
845 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
846 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
847 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
848 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
849 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
850 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
851 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
852 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
853 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
854 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
855 >;
856 };
857
858 pinctrl_usb_hub: usb-hub-grp {
859 fsl,pins = <
860 /* USBHUB_RESET# */
861 MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x4
862 >;
863 };
864
865 pinctrl_usb1: usb1-grp {
866 fsl,pins = <
867 MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x6
868 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x80
869 >;
870 };
871
872 pinctrl_watchdog_gpio: watchdog-gpio-grp {
873 fsl,pins = <
874 /* WDOG_B# */
875 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x26
876 /* WDOG_EN -- ungate WDT RESET# signal propagation */
877 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x6
878 /* WDOG_KICK# / WDI */
879 MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26
880 >;
881 };
882};
883
884&pwm1 {
885 pinctrl-names = "default";
886 pinctrl-0 = <&pinctrl_panel_pwm>;
887 /* Disabled by default, unless display board plugged in. */
888 status = "disabled";
889};
890
891/* SD slot */
892&usdhc2 {
893 pinctrl-names = "default", "state_100mhz", "state_200mhz";
894 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
895 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
896 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
897 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
898 vmmc-supply = <&reg_usdhc2_vmmc>;
899 bus-width = <4>;
900 status = "okay";
901};
902
903/* eMMC */
904&usdhc3 {
905 pinctrl-names = "default", "state_100mhz", "state_200mhz";
906 pinctrl-0 = <&pinctrl_usdhc3>;
907 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
908 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
909 vmmc-supply = <&buck4>;
910 vqmmc-supply = <&buck5>;
911 bus-width = <8>;
912 non-removable;
913 status = "okay";
914};
915
916&uart1 { /* RS485 */
917 pinctrl-names = "default";
918 pinctrl-0 = <&pinctrl_uart1>;
919 uart-has-rtscts;
920 status = "disabled"; /* Optional */
921};
922
923&uart2 {
924 pinctrl-names = "default";
925 pinctrl-0 = <&pinctrl_uart2>;
926 uart-has-rtscts;
927 status = "okay";
928};
929
930&uart3 { /* A53 Debug */
931 pinctrl-names = "default";
932 pinctrl-0 = <&pinctrl_uart3>;
933 status = "okay";
934};
935
936&uart4 {
937 pinctrl-names = "default";
938 pinctrl-0 = <&pinctrl_uart4>;
939 status = "okay";
940};
941
942&usb3_phy0 {
943 status = "okay";
944};
945
946&usb3_0 {
947 fsl,over-current-active-low;
948 status = "okay";
949};
950
951&usb_dwc3_0 { /* Lower plug direct */
952 pinctrl-names = "default";
953 pinctrl-0 = <&pinctrl_usb1>;
954 dr_mode = "host";
955 status = "okay";
956};
957
958&usb3_phy1 {
959 status = "okay";
960};
961
962&usb3_1 {
963 status = "okay";
964};
965
966&usb_dwc3_1 { /* Upper plug via HUB */
967 dr_mode = "host";
968 status = "okay";
969};
970
971&wdog1 {
972 status = "okay";
973};