Ricardo Ribalda Delgado | f84496a | 2008-09-01 13:09:39 -0400 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
Ricardo Ribalda Delgado | 5712d04 | 2016-01-26 11:24:08 +0100 | [diff] [blame] | 3 | * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com |
Ricardo Ribalda Delgado | f84496a | 2008-09-01 13:09:39 -0400 | [diff] [blame] | 4 | * This work has been supported by: QTechnology http://qtec.com/ |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Ricardo Ribalda Delgado | f84496a | 2008-09-01 13:09:39 -0400 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <config.h> |
| 10 | #include <common.h> |
Ricardo Ribalda Delgado | 3f355dd | 2016-01-26 13:47:45 +0100 | [diff] [blame] | 11 | #include <netdev.h> |
Ricardo Ribalda Delgado | f84496a | 2008-09-01 13:09:39 -0400 | [diff] [blame] | 12 | #include <asm/processor.h> |
| 13 | |
Ricardo Ribalda Delgado | 5db1f9d | 2016-01-26 11:24:21 +0100 | [diff] [blame] | 14 | int checkboard(void) |
Ricardo Ribalda Delgado | f84496a | 2008-09-01 13:09:39 -0400 | [diff] [blame] | 15 | { |
| 16 | puts("Xilinx PPC440 Generic Board\n"); |
| 17 | return 0; |
| 18 | } |
Ricardo Ribalda Delgado | f84496a | 2008-09-01 13:09:39 -0400 | [diff] [blame] | 19 | |
Simon Glass | b4de3f3 | 2017-03-31 08:40:24 -0600 | [diff] [blame^] | 20 | phys_size_t initdram(void) |
Ricardo Ribalda Delgado | f84496a | 2008-09-01 13:09:39 -0400 | [diff] [blame] | 21 | { |
| 22 | return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 23 | CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); |
Ricardo Ribalda Delgado | f84496a | 2008-09-01 13:09:39 -0400 | [diff] [blame] | 24 | } |
Ricardo Ribalda Delgado | f84496a | 2008-09-01 13:09:39 -0400 | [diff] [blame] | 25 | |
Ricardo Ribalda Delgado | 5db1f9d | 2016-01-26 11:24:21 +0100 | [diff] [blame] | 26 | void get_sys_info(sys_info_t *sys_info) |
Ricardo Ribalda Delgado | f84496a | 2008-09-01 13:09:39 -0400 | [diff] [blame] | 27 | { |
Ricardo Ribalda Delgado | 5db1f9d | 2016-01-26 11:24:21 +0100 | [diff] [blame] | 28 | sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; |
| 29 | sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; |
| 30 | sys_info->freqPCI = 0; |
Ricardo Ribalda Delgado | f84496a | 2008-09-01 13:09:39 -0400 | [diff] [blame] | 31 | |
| 32 | return; |
| 33 | } |
Ricardo Ribalda Delgado | 4f40e13 | 2016-01-26 11:24:19 +0100 | [diff] [blame] | 34 | |
| 35 | int get_serial_clock(void){ |
| 36 | return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; |
| 37 | } |
Ricardo Ribalda Delgado | 3f355dd | 2016-01-26 13:47:45 +0100 | [diff] [blame] | 38 | |
| 39 | int board_eth_init(bd_t *bis) |
| 40 | { |
| 41 | int ret = 0; |
| 42 | |
| 43 | puts("Init xilinx temac\n"); |
| 44 | #ifdef XPAR_LLTEMAC_0_BASEADDR |
| 45 | ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR, |
| 46 | XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB, |
| 47 | XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR); |
| 48 | |
| 49 | #endif |
| 50 | |
| 51 | #ifdef XPAR_LLTEMAC_1_BASEADDR |
| 52 | ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR, |
| 53 | XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB, |
| 54 | XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR); |
| 55 | #endif |
| 56 | |
| 57 | return ret; |
| 58 | } |