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Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -04001/*
2 * (C) Copyright 2008
Ricardo Ribalda Delgado5712d042016-01-26 11:24:08 +01003 * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -04004 * This work has been supported by: QTechnology http://qtec.com/
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -04007*/
8
9#include <config.h>
10#include <common.h>
Ricardo Ribalda Delgado3f355dd2016-01-26 13:47:45 +010011#include <netdev.h>
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040012#include <asm/processor.h>
13
Ricardo Ribalda Delgado5db1f9d2016-01-26 11:24:21 +010014int checkboard(void)
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040015{
16 puts("Xilinx PPC440 Generic Board\n");
17 return 0;
18}
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040019
Simon Glassb4de3f32017-03-31 08:40:24 -060020phys_size_t initdram(void)
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040021{
22 return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020023 CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040024}
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040025
Ricardo Ribalda Delgado5db1f9d2016-01-26 11:24:21 +010026void get_sys_info(sys_info_t *sys_info)
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040027{
Ricardo Ribalda Delgado5db1f9d2016-01-26 11:24:21 +010028 sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
29 sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
30 sys_info->freqPCI = 0;
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040031
32 return;
33}
Ricardo Ribalda Delgado4f40e132016-01-26 11:24:19 +010034
35int get_serial_clock(void){
36 return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
37}
Ricardo Ribalda Delgado3f355dd2016-01-26 13:47:45 +010038
39int board_eth_init(bd_t *bis)
40{
41 int ret = 0;
42
43 puts("Init xilinx temac\n");
44#ifdef XPAR_LLTEMAC_0_BASEADDR
45 ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR,
46 XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
47 XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR);
48
49#endif
50
51#ifdef XPAR_LLTEMAC_1_BASEADDR
52 ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR,
53 XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
54 XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR);
55#endif
56
57 return ret;
58}