| Marek Vasut | 32ada57 | 2015-08-01 21:35:18 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Marek Vasut <marex@denx.de> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <errno.h> |
| 9 | #include <asm/arch/sdram.h> |
| 10 | /* QTS output file. */ |
| 11 | #include "qts/sdram_config.h" |
| 12 | |
| Marek Vasut | 3384e74 | 2015-08-02 17:15:19 +0200 | [diff] [blame^] | 13 | #include "qts/sequencer_auto_ac_init.h" |
| 14 | #include "qts/sequencer_auto_inst_init.h" |
| 15 | |
| Marek Vasut | 32ada57 | 2015-08-01 21:35:18 +0200 | [diff] [blame] | 16 | static const struct socfpga_sdram_config sdram_config = { |
| 17 | .ctrl_cfg = |
| 18 | (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << |
| 19 | SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) | |
| 20 | (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << |
| 21 | SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) | |
| 22 | (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER << |
| 23 | SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) | |
| 24 | (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << |
| 25 | SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) | |
| 26 | (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << |
| 27 | SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) | |
| 28 | (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << |
| 29 | SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) | |
| 30 | (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << |
| 31 | SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) | |
| 32 | (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << |
| 33 | SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) | |
| 34 | (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << |
| 35 | SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB), |
| 36 | .dram_timing1 = |
| 37 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << |
| 38 | SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) | |
| 39 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << |
| 40 | SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) | |
| 41 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << |
| 42 | SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) | |
| 43 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << |
| 44 | SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) | |
| 45 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << |
| 46 | SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) | |
| 47 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << |
| 48 | SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB), |
| 49 | .dram_timing2 = |
| 50 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << |
| 51 | SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) | |
| 52 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << |
| 53 | SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) | |
| 54 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << |
| 55 | SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) | |
| 56 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << |
| 57 | SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) | |
| 58 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << |
| 59 | SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB), |
| 60 | .dram_timing3 = |
| 61 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << |
| 62 | SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) | |
| 63 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << |
| 64 | SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) | |
| 65 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << |
| 66 | SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) | |
| 67 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << |
| 68 | SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) | |
| 69 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << |
| 70 | SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB), |
| 71 | .dram_timing4 = |
| 72 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << |
| 73 | SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) | |
| 74 | (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << |
| 75 | SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB), |
| 76 | .lowpwr_timing = |
| 77 | (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << |
| 78 | SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) | |
| 79 | (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << |
| 80 | SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB), |
| 81 | .dram_odt = |
| 82 | (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ << |
| 83 | SDR_CTRLGRP_DRAMODT_READ_LSB) | |
| 84 | (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << |
| 85 | SDR_CTRLGRP_DRAMODT_WRITE_LSB), |
| 86 | .dram_addrw = |
| 87 | (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << |
| 88 | SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | |
| 89 | (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS << |
| 90 | SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) | |
| 91 | (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << |
| 92 | SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) | |
| 93 | ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << |
| 94 | SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB), |
| 95 | .dram_if_width = |
| 96 | (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH << |
| 97 | SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB), |
| 98 | .dram_dev_width = |
| 99 | (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH << |
| 100 | SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB), |
| 101 | .dram_intr = |
| 102 | (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << |
| 103 | SDR_CTRLGRP_DRAMINTR_INTREN_LSB), |
| 104 | .lowpwr_eq = |
| 105 | (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK << |
| 106 | SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB), |
| 107 | .static_cfg = |
| 108 | (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << |
| 109 | SDR_CTRLGRP_STATICCFG_MEMBL_LSB) | |
| 110 | (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << |
| 111 | SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB), |
| 112 | .ctrl_width = |
| 113 | (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH << |
| 114 | SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB), |
| 115 | .cport_width = |
| 116 | (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << |
| 117 | SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB), |
| 118 | .cport_wmap = |
| 119 | (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << |
| 120 | SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB), |
| 121 | .cport_rmap = |
| 122 | (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << |
| 123 | SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB), |
| 124 | .rfifo_cmap = |
| 125 | (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << |
| 126 | SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB), |
| 127 | .wfifo_cmap = |
| 128 | (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << |
| 129 | SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB), |
| 130 | .cport_rdwr = |
| 131 | (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << |
| 132 | SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB), |
| 133 | .port_cfg = |
| 134 | (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << |
| 135 | SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB), |
| 136 | .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST, |
| 137 | .fifo_cfg = |
| 138 | (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << |
| 139 | SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) | |
| 140 | (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << |
| 141 | SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB), |
| 142 | .mp_priority = |
| 143 | (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << |
| 144 | SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB), |
| 145 | .mp_weight0 = |
| 146 | (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << |
| 147 | SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB), |
| 148 | .mp_weight1 = |
| 149 | (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << |
| 150 | SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) | |
| 151 | (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << |
| 152 | SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB), |
| 153 | .mp_weight2 = |
| 154 | (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << |
| 155 | SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB), |
| 156 | .mp_weight3 = |
| 157 | (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << |
| 158 | SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB), |
| 159 | .mp_pacing0 = |
| 160 | (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << |
| 161 | SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB), |
| 162 | .mp_pacing1 = |
| 163 | (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << |
| 164 | SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) | |
| 165 | (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 << |
| 166 | SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB), |
| 167 | .mp_pacing2 = |
| 168 | (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << |
| 169 | SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB), |
| 170 | .mp_pacing3 = |
| 171 | (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << |
| 172 | SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB), |
| 173 | .mp_threshold0 = |
| 174 | (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << |
| 175 | SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB), |
| 176 | .mp_threshold1 = |
| 177 | (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << |
| 178 | SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB), |
| 179 | .mp_threshold2 = |
| 180 | (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << |
| 181 | SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB), |
| 182 | .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0, |
| 183 | }; |
| 184 | |
| 185 | const struct socfpga_sdram_config *socfpga_get_sdram_config(void) |
| 186 | { |
| 187 | return &sdram_config; |
| 188 | } |
| Marek Vasut | 3384e74 | 2015-08-02 17:15:19 +0200 | [diff] [blame^] | 189 | |
| 190 | void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem) |
| 191 | { |
| 192 | *init = ac_rom_init; |
| 193 | *nelem = ARRAY_SIZE(ac_rom_init); |
| 194 | } |
| 195 | |
| 196 | void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem) |
| 197 | { |
| 198 | *init = inst_rom_init; |
| 199 | *nelem = ARRAY_SIZE(inst_rom_init); |
| 200 | } |