Jernej Skrabec | 463304d | 2021-01-06 18:02:56 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | // Copyright (C) 2020 Ondrej Jirman <megous@megous.com> |
| 3 | // Copyright (C) 2020 Clément Péron <peron.clem@gmail.com> |
| 4 | |
| 5 | / { |
Samuel Holland | 399a01f | 2022-04-27 15:31:31 -0500 | [diff] [blame^] | 6 | cpu_opp_table: opp-table-cpu { |
Jernej Skrabec | 463304d | 2021-01-06 18:02:56 +0100 | [diff] [blame] | 7 | compatible = "allwinner,sun50i-h6-operating-points"; |
| 8 | nvmem-cells = <&cpu_speed_grade>; |
| 9 | opp-shared; |
| 10 | |
Andre Przywara | 787f5a0 | 2021-05-25 01:20:25 +0100 | [diff] [blame] | 11 | opp-480000000 { |
Jernej Skrabec | 463304d | 2021-01-06 18:02:56 +0100 | [diff] [blame] | 12 | clock-latency-ns = <244144>; /* 8 32k periods */ |
| 13 | opp-hz = /bits/ 64 <480000000>; |
| 14 | |
| 15 | opp-microvolt-speed0 = <880000 880000 1200000>; |
| 16 | opp-microvolt-speed1 = <820000 820000 1200000>; |
| 17 | opp-microvolt-speed2 = <820000 820000 1200000>; |
| 18 | }; |
| 19 | |
Andre Przywara | 787f5a0 | 2021-05-25 01:20:25 +0100 | [diff] [blame] | 20 | opp-720000000 { |
Jernej Skrabec | 463304d | 2021-01-06 18:02:56 +0100 | [diff] [blame] | 21 | clock-latency-ns = <244144>; /* 8 32k periods */ |
| 22 | opp-hz = /bits/ 64 <720000000>; |
| 23 | |
| 24 | opp-microvolt-speed0 = <880000 880000 1200000>; |
| 25 | opp-microvolt-speed1 = <820000 820000 1200000>; |
| 26 | opp-microvolt-speed2 = <820000 820000 1200000>; |
| 27 | }; |
| 28 | |
Andre Przywara | 787f5a0 | 2021-05-25 01:20:25 +0100 | [diff] [blame] | 29 | opp-816000000 { |
Jernej Skrabec | 463304d | 2021-01-06 18:02:56 +0100 | [diff] [blame] | 30 | clock-latency-ns = <244144>; /* 8 32k periods */ |
| 31 | opp-hz = /bits/ 64 <816000000>; |
| 32 | |
| 33 | opp-microvolt-speed0 = <880000 880000 1200000>; |
| 34 | opp-microvolt-speed1 = <820000 820000 1200000>; |
| 35 | opp-microvolt-speed2 = <820000 820000 1200000>; |
| 36 | }; |
| 37 | |
Andre Przywara | 787f5a0 | 2021-05-25 01:20:25 +0100 | [diff] [blame] | 38 | opp-888000000 { |
Jernej Skrabec | 463304d | 2021-01-06 18:02:56 +0100 | [diff] [blame] | 39 | clock-latency-ns = <244144>; /* 8 32k periods */ |
| 40 | opp-hz = /bits/ 64 <888000000>; |
| 41 | |
| 42 | opp-microvolt-speed0 = <880000 880000 1200000>; |
| 43 | opp-microvolt-speed1 = <820000 820000 1200000>; |
| 44 | opp-microvolt-speed2 = <820000 820000 1200000>; |
| 45 | }; |
| 46 | |
Andre Przywara | 787f5a0 | 2021-05-25 01:20:25 +0100 | [diff] [blame] | 47 | opp-1080000000 { |
Jernej Skrabec | 463304d | 2021-01-06 18:02:56 +0100 | [diff] [blame] | 48 | clock-latency-ns = <244144>; /* 8 32k periods */ |
| 49 | opp-hz = /bits/ 64 <1080000000>; |
| 50 | |
| 51 | opp-microvolt-speed0 = <940000 940000 1200000>; |
| 52 | opp-microvolt-speed1 = <880000 880000 1200000>; |
| 53 | opp-microvolt-speed2 = <880000 880000 1200000>; |
| 54 | }; |
| 55 | |
Andre Przywara | 787f5a0 | 2021-05-25 01:20:25 +0100 | [diff] [blame] | 56 | opp-1320000000 { |
Jernej Skrabec | 463304d | 2021-01-06 18:02:56 +0100 | [diff] [blame] | 57 | clock-latency-ns = <244144>; /* 8 32k periods */ |
| 58 | opp-hz = /bits/ 64 <1320000000>; |
| 59 | |
| 60 | opp-microvolt-speed0 = <1000000 1000000 1200000>; |
| 61 | opp-microvolt-speed1 = <940000 940000 1200000>; |
| 62 | opp-microvolt-speed2 = <940000 940000 1200000>; |
| 63 | }; |
| 64 | |
Andre Przywara | 787f5a0 | 2021-05-25 01:20:25 +0100 | [diff] [blame] | 65 | opp-1488000000 { |
Jernej Skrabec | 463304d | 2021-01-06 18:02:56 +0100 | [diff] [blame] | 66 | clock-latency-ns = <244144>; /* 8 32k periods */ |
| 67 | opp-hz = /bits/ 64 <1488000000>; |
| 68 | |
| 69 | opp-microvolt-speed0 = <1060000 1060000 1200000>; |
| 70 | opp-microvolt-speed1 = <1000000 1000000 1200000>; |
| 71 | opp-microvolt-speed2 = <1000000 1000000 1200000>; |
| 72 | }; |
| 73 | |
Andre Przywara | 787f5a0 | 2021-05-25 01:20:25 +0100 | [diff] [blame] | 74 | opp-1608000000 { |
Jernej Skrabec | 463304d | 2021-01-06 18:02:56 +0100 | [diff] [blame] | 75 | clock-latency-ns = <244144>; /* 8 32k periods */ |
| 76 | opp-hz = /bits/ 64 <1608000000>; |
| 77 | |
| 78 | opp-microvolt-speed0 = <1090000 1090000 1200000>; |
| 79 | opp-microvolt-speed1 = <1030000 1030000 1200000>; |
| 80 | opp-microvolt-speed2 = <1030000 1030000 1200000>; |
| 81 | }; |
| 82 | |
Andre Przywara | 787f5a0 | 2021-05-25 01:20:25 +0100 | [diff] [blame] | 83 | opp-1704000000 { |
Jernej Skrabec | 463304d | 2021-01-06 18:02:56 +0100 | [diff] [blame] | 84 | clock-latency-ns = <244144>; /* 8 32k periods */ |
| 85 | opp-hz = /bits/ 64 <1704000000>; |
| 86 | |
| 87 | opp-microvolt-speed0 = <1120000 1120000 1200000>; |
| 88 | opp-microvolt-speed1 = <1060000 1060000 1200000>; |
| 89 | opp-microvolt-speed2 = <1060000 1060000 1200000>; |
| 90 | }; |
| 91 | |
Andre Przywara | 787f5a0 | 2021-05-25 01:20:25 +0100 | [diff] [blame] | 92 | opp-1800000000 { |
Jernej Skrabec | 463304d | 2021-01-06 18:02:56 +0100 | [diff] [blame] | 93 | clock-latency-ns = <244144>; /* 8 32k periods */ |
| 94 | opp-hz = /bits/ 64 <1800000000>; |
| 95 | |
| 96 | opp-microvolt-speed0 = <1160000 1160000 1200000>; |
| 97 | opp-microvolt-speed1 = <1100000 1100000 1200000>; |
| 98 | opp-microvolt-speed2 = <1100000 1100000 1200000>; |
| 99 | }; |
| 100 | }; |
| 101 | }; |
| 102 | |
| 103 | &cpu0 { |
| 104 | operating-points-v2 = <&cpu_opp_table>; |
| 105 | }; |
| 106 | |
| 107 | &cpu1 { |
| 108 | operating-points-v2 = <&cpu_opp_table>; |
| 109 | }; |
| 110 | |
| 111 | &cpu2 { |
| 112 | operating-points-v2 = <&cpu_opp_table>; |
| 113 | }; |
| 114 | |
| 115 | &cpu3 { |
| 116 | operating-points-v2 = <&cpu_opp_table>; |
| 117 | }; |