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git01.mediatek.com / filogic / uboot / 388ef184770941e596aef41d281d0c5d15c0a46f / . / arch / arm / dts / at91-sam9x60_curiosity-u-boot.dtsi
blob: dd4623311c9df6004c1715d406d3873bbcc254b5 [file] [log] [blame]
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * at91-sam9x60_curiosity-u-boot.dtsi - Device Tree Include file for SAM9X60
4 * CURIOSITY.
5 *
6 * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
7 *
8 * Author: Durai Manickam KR <durai.manickamkr@microchip.com>
9 */
10
11/ {
12 ahb {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]13 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]14
15 apb {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]16 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]17 };
18 };
19
20 chosen {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]22 };
Alexander Dahl23f626d2023-08-23 15:58:55 +0200[diff] [blame]23
24 config {
25 u-boot,boot-led = "blue";
26 };
27
28 leds {
29 led-red {
30 default-state = "off";
31 };
32
33 led-green {
34 default-state = "off";
35 };
36
37 led-blue {
38 default-state = "off";
39 };
40 };
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]41};
42
43&clk32 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]45};
46
47&dbgu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]49};
50
51&main_rc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]53};
54
55&main_xtal {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]57};
58
Alexander Dahl5c3e8672023-07-05 22:17:00 +0200[diff] [blame]59&pinctrl {
60 bootph-all;
61};
62
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]63&pinctrl_dbgu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]65};
66
67&pinctrl_sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]69};
70
71&pioA {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]73};
74
75&pioB {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]77};
78
79&pit64b0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]81};
82
83&pmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]85};
86
87&sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]89};
90
91&slow_rc_osc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]93};
94
95&slow_xtal {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-all;
Durai Manickam KRa0509712022-04-04 11:23:19 +0530[diff] [blame]97};