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git01.mediatek.com / filogic / uboot / 164e3874986ce479e17af0824238746c556f2d76 / . / include / asm-ppc / immap_86xx.h
blob: 9e81b47071649f430344894a9eeebadd3bf1ec7b [file] [log] [blame]
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500[diff] [blame]1/*
2 * MPC86xx Internal Memory Map
3 *
4 * Copyright(c) 2004 Freescale Semiconductor
5 * Jeff Brown (Jeffrey@freescale.com)
6 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
7 *
8 */
9
10#ifndef __IMMAP_86xx__
11#define __IMMAP_86xx__
12
13
14/* Local-Access Registers and MCM Registers(0x0000-0x2000) */
15typedef struct ccsr_local_mcm {
16 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
17 char res1[4];
18 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
19 char res2[4];
20 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
21 char res3[12];
22 uint bptr; /* 0x20 - Boot Page Translation Register */
23 char res4[3044];
24 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
25 char res5[4];
26 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
27 char res6[20];
28 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
29 char res7[4];
30 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
31 char res8[20];
32 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
33 char res9[4];
34 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
35 char res10[20];
36 uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
37 char res11[4];
38 uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
39 char res12[20];
40 uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
41 char res13[4];
42 uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
43 char res14[20];
44 uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
45 char res15[4];
46 uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
47 char res16[20];
48 uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
49 char res17[4];
50 uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
51 char res18[20];
52 uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
53 char res19[4];
54 uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
Jon Loeliger20836d42006-05-19 13:22:44 -0500[diff] [blame]55 char res20[20];
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500[diff] [blame]56 uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
57 char res21[4];
58 uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
59 char res22[20];
60 uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
61 char res23[4];
62 uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
Jon Loeliger20836d42006-05-19 13:22:44 -0500[diff] [blame]63 char res24[716];
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500[diff] [blame]64 uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */
65 char res25[4];
66 uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */
67 char res26[4];
68 uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */
69 char res27[44];
70 uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */
71 uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */
72 uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */
73 uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */
74 char res28[16];
75 uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */
76 uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */
77 uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */
78 char res29[3476];
79 uint edr; /* 0x1e00 - MCM Error Detect Register */
80 char res30[4];
81 uint eer; /* 0x1e08 - MCM Error Enable Register */
82 uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */
83 uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */
84 uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */
85 char res31[488];
86} ccsr_local_mcm_t;
87
88/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */
89
90typedef struct ccsr_ddr {
91 uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
92 char res1[4];
93 uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
94 char res2[4];
95 uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
96 char res3[4];
97 uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
98 char res4[4];
99 uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */
100 char res5[4];
101 uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */
102 char res6[84];
103 uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
104 uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
105 uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
106 uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
107 uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */
108 uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */
109 char res7[104];
110 uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */
111 uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
112 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
113 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
114 uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */
115 uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
116 uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
117 uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
118 uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
119 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
120 uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */
121 char res8[4];
122 uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
123 char res9[12];
124 uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */
125 uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */
126 uint init_addr; /* 0x2148 - DDR training initialzation address */
127 uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */
128 char res10[2728];
129 uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
130 uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
131 char res11[512];
132 uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
133 uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
134 uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
135 char res12[20];
136 uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
137 uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
138 uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
139 char res13[20];
140 uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
141 uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
142 uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */
143 uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
144 uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
145 uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
146 uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
147 char res14[164];
148 uint debug_1; /* 0x2f00 */
149 uint debug_2;
150 uint debug_3;
151 uint debug_4;
152 uint debug_5;
153 char res15[236];
154} ccsr_ddr_t;
155
156
157/* Daul I2C Registers(0x3000-0x4000) */
158
159typedef struct ccsr_i2c {
160 u_char i2cadr1; /* 0x3000 - I2C 1 Address Register */
161#define MPC86xx_I2CADR_MASK 0xFE
162 char res1[3];
163 u_char i2cfdr1; /* 0x3004 - I2C 1 Frequency Divider Register */
164#define MPC86xx_I2CFDR_MASK 0x3F
165 char res2[3];
166 u_char i2ccr1; /* 0x3008 - I2C 1 Control Register */
167#define MPC86xx_I2CCR_MEN 0x80
168#define MPC86xx_I2CCR_MIEN 0x40
169#define MPC86xx_I2CCR_MSTA 0x20
170#define MPC86xx_I2CCR_MTX 0x10
171#define MPC86xx_I2CCR_TXAK 0x08
172#define MPC86xx_I2CCR_RSTA 0x04
173#define MPC86xx_I2CCR_BCST 0x01
174 char res3[3];
175 u_char i2csr1; /* 0x300c - I2C 1 Status Register */
176#define MPC86xx_I2CSR_MCF 0x80
177#define MPC86xx_I2CSR_MAAS 0x40
178#define MPC86xx_I2CSR_MBB 0x20
179#define MPC86xx_I2CSR_MAL 0x10
180#define MPC86xx_I2CSR_BCSTM 0x08
181#define MPC86xx_I2CSR_SRW 0x04
182#define MPC86xx_I2CSR_MIF 0x02
183#define MPC86xx_I2CSR_RXAK 0x01
184 char res4[3];
185 u_char i2cdr1; /* 0x3010 - I2C 1 Data Register */
186#define MPC86xx_I2CDR_DATA 0xFF
187 char res5[3];
188 u_char i2cdfsrr1; /* 0x3014 - I2C 1 Digital Filtering Sampling Rate Register */
189#define MPC86xx_I2CDFSRR 0x3F
190 char res6[235];
191
192 u_char i2cadr2; /* 0x3100 - I2C 2 Address Register */
193 char res7[3];
194 u_char i2cfdr2; /* 0x3104 - I2C 2 Frequency Divider Register */
195 char res8[3];
196 u_char i2ccr2; /* 0x3108 - I2C 2 Control Register */
197 char res9[3];
198 u_char i2csr2; /* 0x310c - I2C 2 Status Register */
199 char res10[3];
200 u_char i2cdr2; /* 0x3110 - I2C 2 Data Register */
201 char res11[3];
202 u_char i2cdfsrr2; /* 0x3114 - I2C 2 Digital Filtering Sampling Rate Register */
203 char res12[3819];
204} ccsr_i2c_t;
205
206/* DUART Registers(0x4000-0x5000) */
207typedef struct ccsr_duart {
208 char res1[1280];
209 u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
210 u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
211 u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
212 u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
213 u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
214 u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
215 u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
216 u_char uscr1; /* 0x4507 - UART1 Scratch Register */
217 char res2[8];
218 u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
219 char res3[239];
220 u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
221 u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
222 u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
223 u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
224 u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
225 u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
226 u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
227 u_char uscr2; /* 0x4607 - UART2 Scratch Register */
228 char res4[8];
229 u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
230 char res5[2543];
231} ccsr_duart_t;
232
233
234/* Local Bus Controller Registers(0x5000-0x6000) */
235typedef struct ccsr_lbc {
236 uint br0; /* 0x5000 - LBC Base Register 0 */
237 uint or0; /* 0x5004 - LBC Options Register 0 */
238 uint br1; /* 0x5008 - LBC Base Register 1 */
239 uint or1; /* 0x500c - LBC Options Register 1 */
240 uint br2; /* 0x5010 - LBC Base Register 2 */
241 uint or2; /* 0x5014 - LBC Options Register 2 */
242 uint br3; /* 0x5018 - LBC Base Register 3 */
243 uint or3; /* 0x501c - LBC Options Register 3 */
244 uint br4; /* 0x5020 - LBC Base Register 4 */
245 uint or4; /* 0x5024 - LBC Options Register 4 */
246 uint br5; /* 0x5028 - LBC Base Register 5 */
247 uint or5; /* 0x502c - LBC Options Register 5 */
248 uint br6; /* 0x5030 - LBC Base Register 6 */
249 uint or6; /* 0x5034 - LBC Options Register 6 */
250 uint br7; /* 0x5038 - LBC Base Register 7 */
251 uint or7; /* 0x503c - LBC Options Register 7 */
252 char res1[40];
253 uint mar; /* 0x5068 - LBC UPM Address Register */
254 char res2[4];
255 uint mamr; /* 0x5070 - LBC UPMA Mode Register */
256 uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
257 uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
258 char res3[8];
259 uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
260 uint mdr; /* 0x5088 - LBC UPM Data Register */
261 char res4[8];
262 uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
263 char res5[8];
264 uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
265 uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
266 char res6[8];
267 uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
268 uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
269 uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
270 uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
271 uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
272 char res7[12];
273 uint lbcr; /* 0x50d0 - LBC Configuration Register */
274 uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
275 char res8[3880];
276} ccsr_lbc_t;
277
278/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
279typedef struct ccsr_pex {
280 uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
281 uint cfg_data; /* 0x8004 - PEX Configuration Data Register */
282 char res1[4];
283 uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */
284 char res2[16];
285 uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */
286 uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */
287 uint pme_msg_dis; /* 0x802C - PEX PME & message disable register */
288 char res3[4];
289 uint pm_command; /* 0x8030 - PEX PM Command register */
290 char res4[3016];
291 uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */
292 uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */
293 uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
294 uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
295 char res5[8];
296 uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
297 char res6[12];
298 uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
299 uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
300 uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */
301 char res7[4];
302 uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
303 char res8[12];
304 uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
305 uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
306 uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */
307 char res9[4];
308 uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
309 char res10[12];
310 uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
311 uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
312 uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */
313 char res11[4];
314 uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
315 char res12[12];
316 uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
317 uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
318 uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */
319 char res13[4];
320 uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
321 char res14[268];
322 uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */
323 char res15[4];
324 uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */
325 uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
326 uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
327 char res16[12];
328 uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */
329 char res17[4];
330 uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
331 uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
332 uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
333 char res18[12];
334 uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */
335 char res19[4];
336 uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */
337 char res20[4];
338 uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
339 char res21[12];
340 uint pedr; /* 0x8e00 - PEX Error Detect Register */
341 uint pecdr; /* 0x8e04 - PEX Error Capture Disable Register */
342 uint peer; /* 0x8e08 - PEX Error Enable Register */
343 uint perr_cap0; /* 0x8e0c - PEX Error Capture Register 0 */
344 uint perr_cap1; /* 0x8e10 - PEX Error Capture Register 1 */
345 uint perr_cap2; /* 0x8e14 - PEX Error Capture Register 2 */
346 uint perr_cap3; /* 0x8e18 - PEX Error Capture Register 3 */
347 char res22[100];
348 uint perr_stat; /* 0x8e80 - PEX Error Status Register */
349 char res23[124];
350 uint pdebug; /* 0x8f00 - PEX Debug Register */
351 char res24[248]; //Sri: changed this because of adding 4 bytes before 0x?8020.
352} ccsr_pex_t;
353
354/* Hyper Transport Register Block (0xA000-0xB000) */
355typedef struct ccsr_ht {
356 uint hcfg_addr; /* 0xa000 - HT Configuration Address register */
357 uint hcfg_data; /* 0xa004 - HT Configuration Data register */
358 char res1[3064];
359 uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */
360 char res2[12];
361 uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */
362 char res3[12];
363 uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */
364 char res4[4];
365 uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */
366 char res5[4];
367 uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */
368 char res6[12];
369 uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */
370 char res7[4];
371 uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */
372 char res8[4];
373 uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */
374 char res9[12];
375 uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */
376 char res10[4];
377 uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */
378 char res11[4];
379 uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */
380 char res12[12];
381 uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */
382 char res13[4];
383 uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */
384 char res14[4];
385 uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */
386 char res15[236];
387 uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */
388 char res16[4];
389 uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */
390 char res17[4];
391 uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */
392 char res18[12];
393 uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */
394 char res19[4];
395 uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */
396 char res20[4];
397 uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */
398 char res21[12];
399 uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */
400 char res22[4];
401 uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */
402 char res23[4];
403 uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */
404 char res24[12];
405 uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */
406 char res25[4];
407 uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */
408 char res26[4];
409 uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */
410 char res27[12];
411 uint hedr; /* 0xae00 - HT Error Detect register */
412 char res28[4];
413 uint heier; /* 0xae08 - HT Error Interrupt Enable register */
414 char res29[4];
415 uint hecdr; /* 0xae10 - HT Error Capture Disbale register */
416 char res30[12];
417 uint hecsr; /* 0xae20 - HT Error Capture Status register */
418 char res31[4];
419 uint hec0; /* 0xae28 - HT Error Capture 0 register */
420 uint hec1; /* 0xae2c - HT Error Capture 1 register */
421 uint hec2; /* 0xae30 - HT Error Capture 2 register */
422 char res32[460];
423} ccsr_ht_t;
424
425/* DMA Registers(0x2_1000-0x2_2000) */
426typedef struct ccsr_dma {
427 char res1[256];
428 uint mr0; /* 0x21100 - DMA 0 Mode Register */
429 uint sr0; /* 0x21104 - DMA 0 Status Register */
430 char res2[4];
431 uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
432 uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */
433 uint sar0; /* 0x21114 - DMA 0 Source Address Register */
434 uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */
435 uint dar0; /* 0x2111c - DMA 0 Destination Address Register */
436 uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */
437 char res3[4];
438 uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
439 char res4[8];
440 uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
441 char res5[4];
442 uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */
443 uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */
444 uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */
445 char res6[56];
446 uint mr1; /* 0x21180 - DMA 1 Mode Register */
447 uint sr1; /* 0x21184 - DMA 1 Status Register */
448 char res7[4];
449 uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
450 uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */
451 uint sar1; /* 0x21194 - DMA 1 Source Address Register */
452 uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */
453 uint dar1; /* 0x2119c - DMA 1 Destination Address Register */
454 uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */
455 char res8[4];
456 uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
457 char res9[8];
458 uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
459 char res10[4];
460 uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */
461 uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */
462 uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */
463 char res11[56];
464 uint mr2; /* 0x21200 - DMA 2 Mode Register */
465 uint sr2; /* 0x21204 - DMA 2 Status Register */
466 char res12[4];
467 uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
468 uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */
469 uint sar2; /* 0x21214 - DMA 2 Source Address Register */
470 uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */
471 uint dar2; /* 0x2121c - DMA 2 Destination Address Register */
472 uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */
473 char res13[4];
474 uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
475 char res14[8];
476 uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
477 char res15[4];
478 uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */
479 uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */
480 uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */
481 char res16[56];
482 uint mr3; /* 0x21280 - DMA 3 Mode Register */
483 uint sr3; /* 0x21284 - DMA 3 Status Register */
484 char res17[4];
485 uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
486 uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */
487 uint sar3; /* 0x21294 - DMA 3 Source Address Register */
488 uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */
489 uint dar3; /* 0x2129c - DMA 3 Destination Address Register */
490 uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */
491 char res18[4];
492 uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
493 char res19[8];
494 uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
495 char res20[4];
496 uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */
497 uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */
498 uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */
499 char res21[56];
500 uint dgsr; /* 0x21300 - DMA General Status Register */
501 char res22[3324];
502} ccsr_dma_t;
503
504/* tsec1-4: 24000-28000 */
505typedef struct ccsr_tsec {
506 uint id; /* 0x24000 - Controller ID Register */
507 char res1[12];
508 uint ievent; /* 0x24010 - Interrupt Event Register */
509 uint imask; /* 0x24014 - Interrupt Mask Register */
510 uint edis; /* 0x24018 - Error Disabled Register */
511 char res2[4];
512 uint ecntrl; /* 0x24020 - Ethernet Control Register */
513 char res2_1[4];
514 uint ptv; /* 0x24028 - Pause Time Value Register */
515 uint dmactrl; /* 0x2402c - DMA Control Register */
516 uint tbipa; /* 0x24030 - TBI PHY Address Register */
517 char res3[88];
518 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
519 char res4[8];
520 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
521 uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
522 char res4_1[4];
523 uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */
524 uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */
525 char res5[84];
526 uint tctrl; /* 0x24100 - Transmit Control Register */
527 uint tstat; /* 0x24104 - Transmit Status Register */
528 uint dfvlan; /* 0x24108 - Default VLAN control word */
529 char res6[4];
530 uint txic; /* 0x24110 - Transmit interrupt coalescing Register */
531 uint tqueue; /* 0x24114 - Transmit Queue Control Register */
532 char res7[40];
533 uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
534 uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
535 char res8[52];
536 uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
537 char res9[4];
538 uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
539 char res10[4];
540 uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
541 char res11[4];
542 uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
543 char res12[4];
544 uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
545 char res13[4];
546 uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
547 char res14[4];
548 uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
549 char res15[4];
550 uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
551 char res16[4];
552 uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
553 char res17[64];
554 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
555 uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
556 char res18[4];
557 uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
558 char res19[4];
559 uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
560 char res20[4];
561 uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
562 char res21[4];
563 uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
564 char res22[4];
565 uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
566 char res23[4];
567 uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
568 char res24[4];
569 uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
570 char res25[192];
571 uint rctrl; /* 0x24300 - Receive Control Register */
572 uint rstat; /* 0x24304 - Receive Status Register */
573 char res26[8];
574 uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */
575 uint rqueue; /* 0x24314 - Receive queue control register */
576 char res27[24];
577 uint rbifx; /* 0x24330 - Receive bit field extract control Register */
578 uint rqfar; /* 0x24334 - Receive queue filing table address Register */
579 uint rqfcr; /* 0x24338 - Receive queue filing table control Register */
580 uint rqfpr; /* 0x2433c - Receive queue filing table property Register */
581 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
582 char res28[56];
583 uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
584 char res29[4];
585 uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
586 char res30[4];
587 uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
588 char res31[4];
589 uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
590 char res32[4];
591 uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
592 char res33[4];
593 uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
594 char res34[4];
595 uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
596 char res35[4];
597 uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
598 char res36[4];
599 uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
600 char res37[64];
601 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
602 uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */
603 char res38[4];
604 uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */
605 char res39[4];
606 uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */
607 char res40[4];
608 uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */
609 char res41[4];
610 uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */
611 char res42[4];
612 uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */
613 char res43[4];
614 uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */
615 char res44[4];
616 uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */
617 char res45[192];
618 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
619 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
620 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
621 uint hafdup; /* 0x2450c - Half Duplex Register */
622 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
623 char res46[12];
624 uint miimcfg; /* 0x24520 - MII Management Configuration Register */
625 uint miimcom; /* 0x24524 - MII Management Command Register */
626 uint miimadd; /* 0x24528 - MII Management Address Register */
627 uint miimcon; /* 0x2452c - MII Management Control Register */
628 uint miimstat; /* 0x24530 - MII Management Status Register */
629 uint miimind; /* 0x24534 - MII Management Indicator Register */
630 uint ifctrl; /* 0x24538 - Interface Contrl Register */
631 uint ifstat; /* 0x2453c - Interface Status Register */
632 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
633 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
634 uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */
635 uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */
636 uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */
637 uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */
638 uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */
639 uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */
640 uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */
641 uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */
642 uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */
643 uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */
644 uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */
645 uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */
646 uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */
647 uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */
648 uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */
649 uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */
650 uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */
651 uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */
652 uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */
653 uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */
654 uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */
655 uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */
656 uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */
657 uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */
658 uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */
659 uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */
660 uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */
661 uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */
662 uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */
663 uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */
664 char res48[192];
665 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
666 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
667 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
668 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
669 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
670 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
671 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
672 uint rbyt; /* 0x2469c - Receive Byte Counter */
673 uint rpkt; /* 0x246a0 - Receive Packet Counter */
674 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
675 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
676 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
677 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
678 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
679 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
680 uint raln; /* 0x246bc - Receive Alignment Error Counter */
681 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
682 uint rcde; /* 0x246c4 - Receive Code Error Counter */
683 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
684 uint rund; /* 0x246cc - Receive Undersize Packet Counter */
685 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
686 uint rfrg; /* 0x246d4 - Receive Fragments Counter */
687 uint rjbr; /* 0x246d8 - Receive Jabber Counter */
688 uint rdrp; /* 0x246dc - Receive Drop Counter */
689 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
690 uint tpkt; /* 0x246e4 - Transmit Packet Counter */
691 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
692 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
693 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
694 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
695 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
696 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
697 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
698 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
699 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
700 uint tncl; /* 0x2470c - Transmit Total Collision Counter */
701 char res49[4];
702 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
703 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
704 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
705 uint txcf; /* 0x24720 - Transmit Control Frame Counter */
706 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
707 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
708 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
709 uint car1; /* 0x24730 - Carry Register One */
710 uint car2; /* 0x24734 - Carry Register Two */
711 uint cam1; /* 0x24738 - Carry Mask Register One */
712 uint cam2; /* 0x2473c - Carry Mask Register Two */
713 uint rrej; /* 0x24740 - Receive filer rejected packet counter */
714 char res50[188];
715 uint iaddr0; /* 0x24800 - Indivdual address register 0 */
716 uint iaddr1; /* 0x24804 - Indivdual address register 1 */
717 uint iaddr2; /* 0x24808 - Indivdual address register 2 */
718 uint iaddr3; /* 0x2480c - Indivdual address register 3 */
719 uint iaddr4; /* 0x24810 - Indivdual address register 4 */
720 uint iaddr5; /* 0x24814 - Indivdual address register 5 */
721 uint iaddr6; /* 0x24818 - Indivdual address register 6 */
722 uint iaddr7; /* 0x2481c - Indivdual address register 7 */
723 char res51[96];
724 uint gaddr0; /* 0x24880 - Global address register 0 */
725 uint gaddr1; /* 0x24884 - Global address register 1 */
726 uint gaddr2; /* 0x24888 - Global address register 2 */
727 uint gaddr3; /* 0x2488c - Global address register 3 */
728 uint gaddr4; /* 0x24890 - Global address register 4 */
729 uint gaddr5; /* 0x24894 - Global address register 5 */
730 uint gaddr6; /* 0x24898 - Global address register 6 */
731 uint gaddr7; /* 0x2489c - Global address register 7 */
732 char res52[352];
733 uint fifocfg; /* 0x24A00 - FIFO interface configuration register */
734 char res53[500];
735 uint attr; /* 0x24BF8 - DMA Attribute register */
736 uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */
737 char res54[1024];
738} ccsr_tsec_t;
739
740/* PIC Registers(0x4_0000-0x6_1000) */
741
742typedef struct ccsr_pic {
743 char res1[64];
744 uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
745 char res2[12];
746 uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
747 char res3[12];
748 uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
749 char res4[12];
750 uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
751 char res5[12];
752 uint ctpr; /* 0x40080 - Current Task Priority Register */
753 char res6[12];
754 uint whoami; /* 0x40090 - Who Am I Register */
755 char res7[12];
756 uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
757 char res8[12];
758 uint eoi; /* 0x400b0 - End Of Interrupt Register */
759 char res9[3916];
760 uint frr; /* 0x41000 - Feature Reporting Register */
761 char res10[28];
762 uint gcr; /* 0x41020 - Global Configuration Register */
763 char res11[92];
764 uint vir; /* 0x41080 - Vendor Identification Register */
765 char res12[12];
766 uint pir; /* 0x41090 - Processor Initialization Register */
767 char res13[12];
768 uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
769 char res14[12];
770 uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
771 char res15[12];
772 uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
773 char res16[12];
774 uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
775 char res17[12];
776 uint svr; /* 0x410e0 - Spurious Vector Register */
777 char res18[12];
778 uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
779 char res19[12];
780 uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
781 char res20[12];
782 uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
783 char res21[12];
784 uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
785 char res22[12];
786 uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
787 char res23[12];
788 uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
789 char res24[12];
790 uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
791 char res25[12];
792 uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
793 char res26[12];
794 uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
795 char res27[12];
796 uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
797 char res28[12];
798 uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
799 char res29[12];
800 uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
801 char res30[12];
802 uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
803 char res31[12];
804 uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
805 char res32[12];
806 uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
807 char res33[12];
808 uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
809 char res34[12];
810 uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
811 char res35[268];
812 uint tcr; /* 0x41300 - Timer Control Register */
813 char res36[12];
814 uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
815 char res37[12];
816 uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
817 char res38[12];
818 uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
819 char res39[12];
820 uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
821 char res40[12];
822 uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */
823 char res41[12];
824 uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */
825 char res42[12];
826 uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */
827 char res43[12];
828 uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */
829 char res44[12];
830 uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */
831 char res45[12];
832 uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */
833 char res46[12];
834 uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */
835 char res47[12];
836 uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */
837 char res48[60];
838 uint msgr0; /* 0x41400 - Message Register 0 */
839 char res49[12];
840 uint msgr1; /* 0x41410 - Message Register 1 */
841 char res50[12];
842 uint msgr2; /* 0x41420 - Message Register 2 */
843 char res51[12];
844 uint msgr3; /* 0x41430 - Message Register 3 */
845 char res52[204];
846 uint mer; /* 0x41500 - Message Enable Register */
847 char res53[12];
848 uint msr; /* 0x41510 - Message Status Register */
849 char res54[60140];
850 uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
851 char res55[12];
852 uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
853 char res56[12];
854 uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
855 char res57[12];
856 uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
857 char res58[12];
858 uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
859 char res59[12];
860 uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
861 char res60[12];
862 uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
863 char res61[12];
864 uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
865 char res62[12];
866 uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
867 char res63[12];
868 uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
869 char res64[12];
870 uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
871 char res65[12];
872 uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
873 char res66[12];
874 uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
875 char res67[12];
876 uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
877 char res68[12];
878 uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
879 char res69[12];
880 uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
881 char res70[12];
882 uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
883 char res71[12];
884 uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
885 char res72[12];
886 uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
887 char res73[12];
888 uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
889 char res74[12];
890 uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
891 char res75[12];
892 uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
893 char res76[12];
894 uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
895 char res77[12];
896 uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
897 char res78[140];
898 uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
899 char res79[12];
900 uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
901 char res80[12];
902 uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
903 char res81[12];
904 uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
905 char res82[12];
906 uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
907 char res83[12];
908 uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
909 char res84[12];
910 uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
911 char res85[12];
912 uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
913 char res86[12];
914 uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
915 char res87[12];
916 uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
917 char res88[12];
918 uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
919 char res89[12];
920 uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
921 char res90[12];
922 uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
923 char res91[12];
924 uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
925 char res92[12];
926 uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
927 char res93[12];
928 uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
929 char res94[12];
930 uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
931 char res95[12];
932 uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
933 char res96[12];
934 uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
935 char res97[12];
936 uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
937 char res98[12];
938 uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
939 char res99[12];
940 uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
941 char res100[12];
942 uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
943 char res101[12];
944 uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
945 char res102[12];
946 uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
947 char res103[12];
948 uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
949 char res104[12];
950 uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
951 char res105[12];
952 uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
953 char res106[12];
954 uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
955 char res107[12];
956 uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
957 char res108[12];
958 uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
959 char res109[12];
960 uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
961 char res110[12];
962 uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
963 char res111[12];
964 uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
965 char res112[12];
966 uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
967 char res113[12];
968 uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
969 char res114[12];
970 uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
971 char res115[12];
972 uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
973 char res116[12];
974 uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
975 char res117[12];
976 uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
977 char res118[12];
978 uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
979 char res119[12];
980 uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
981 char res120[12];
982 uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
983 char res121[12];
984 uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
985 char res122[12];
986 uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
987 char res123[12];
988 uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
989 char res124[12];
990 uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
991 char res125[12];
992 uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
993 char res126[12];
994 uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
995 char res127[12];
996 uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
997 char res128[12];
998 uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
999 char res129[12];
1000 uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
1001 char res130[12];
1002 uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
1003 char res131[12];
1004 uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
1005 char res132[12];
1006 uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
1007 char res133[12];
1008 uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
1009 char res134[12];
1010 uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
1011 char res135[12];
1012 uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
1013 char res136[12];
1014 uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
1015 char res137[12];
1016 uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
1017 char res138[12];
1018 uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
1019 char res139[12];
1020 uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
1021 char res140[12];
1022 uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
1023 char res141[12];
1024 uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
1025 char res142[4108];
1026 uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
1027 char res143[12];
1028 uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
1029 char res144[12];
1030 uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
1031 char res145[12];
1032 uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
1033 char res146[12];
1034 uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
1035 char res147[12];
1036 uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
1037 char res148[12];
1038 uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
1039 char res149[12];
1040 uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
1041 char res150[59852];
1042 uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
1043 char res151[12];
1044 uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
1045 char res152[12];
1046 uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
1047 char res153[12];
1048 uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
1049 char res154[12];
1050 uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
1051 char res155[12];
1052 uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
1053 char res156[12];
1054 uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
1055 char res157[12];
1056 uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
1057 char res158[3916];
1058} ccsr_pic_t;
1059
1060/* RapidIO Registers(0xc_0000-0xe_0000) */
1061
1062typedef struct ccsr_rio {
1063 uint didcar; /* 0xc0000 - Device Identity Capability Register */
1064 uint dicar; /* 0xc0004 - Device Information Capability Register */
1065 uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
1066 uint aicar; /* 0xc000c - Assembly Information Capability Register */
1067 uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
1068 uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
1069 uint socar; /* 0xc0018 - Source Operations Capability Register */
1070 uint docar; /* 0xc001c - Destination Operations Capability Register */
1071 char res1[32];
1072 uint msr; /* 0xc0040 - Mailbox Command And Status Register */
1073 uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
1074 char res2[4];
1075 uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
1076 char res3[12];
1077 uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
1078 uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
1079 char res4[4];
1080 uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
1081 uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
1082 char res5[144];
1083 uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
1084 char res6[28];
1085 uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
1086 uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
1087 char res7[20];
1088 uint pgccsr; /* 0xc013c - Port General Command and Status Register */
1089 uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
1090 uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
1091 uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
1092 char res8[12];
1093 uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
1094 uint pccsr; /* 0xc015c - Port Control Command and Status Register */
1095 char res9[1184];
1096 uint erbh; /* 0xc0600 - Error Reporting Block Header Register */
1097 char res10[4];
1098 uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */
1099 uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */
1100 char res11[4];
1101 uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */
1102 uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */
1103 uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */
1104 char res12[32];
1105 uint edcsr; /* 0xc0640 - Port 0 error detect status register */
1106 uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */
1107 uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */
1108 uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */
1109 uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */
1110 uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */
1111 uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */
1112 char res13[12];
1113 uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */
1114 uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/
1115 char res14[63892];
1116 uint llcr; /* 0xd0004 - Logical Layer Configuration Register */
1117 char res15[12];
1118 uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */
1119 char res16[12];
1120 uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */
1121 char res17[92];
1122 uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
1123 char res18[124];
1124 uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
1125 char res19[28];
1126 uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
1127 char res20[12];
1128 uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */
1129 char res21[12];
1130 uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
1131 char res22[20];
1132 uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */
1133 char res23[4];
1134 uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */
1135 char res24[2716];
1136 uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
1137 uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
1138 char res25[8];
1139 uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
1140 char res26[12];
1141 uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
1142 uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
1143 uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
1144 char res27[4];
1145 uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
1146 uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
1147 uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
1148 uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
1149 uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
1150 uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
1151 uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
1152 char res28[4];
1153 uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
1154 uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
1155 uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
1156 uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
1157 uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
1158 uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
1159 uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
1160 char res29[4];
1161 uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
1162 uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
1163 uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
1164 uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
1165 uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
1166 uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
1167 uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
1168 char res30[4];
1169 uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
1170 uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
1171 uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
1172 uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
1173 uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
1174 uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
1175 uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
1176 char res31[4];
1177 uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
1178 uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
1179 uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
1180 uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
1181 uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
1182 uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
1183 uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
1184 char res32[4];
1185 uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
1186 uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
1187 uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
1188 uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
1189 uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
1190 uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
1191 uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
1192 char res33[4];
1193 uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
1194 uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
1195 uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
1196 uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
1197 uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
1198 uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
1199 uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
1200 char res34[4];
1201 uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
1202 uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
1203 uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
1204 uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
1205 char res35[64];
1206 uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
1207 uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
1208 char res36[4];
1209 uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
1210 char res37[12];
1211 uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
1212 char res38[4];
1213 uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
1214 char res39[4];
1215 uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
1216 char res40[12];
1217 uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1218 char res41[4];
1219 uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1220 char res42[4];
1221 uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1222 char res43[12];
1223 uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1224 char res44[4];
1225 uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1226 char res45[4];
1227 uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1228 char res46[12];
1229 uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1230 char res47[12];
1231 uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1232 char res48[12];
1233 uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1234 uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1235 uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1236 uint pecr; /* 0xd0e0c - Port Error Control Register */
1237 uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1238 uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
1239 uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
1240 char res49[4];
1241 uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
1242 char res50[4];
1243 uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
1244 uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
1245 char res51[8656];
1246 uint omr; /* 0xd3000 - Outbound Mode Register */
1247 uint osr; /* 0xd3004 - Outbound Status Register */
1248 uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1249 uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
1250 uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */
1251 uint osar; /* 0xd3014 - Outbound Unit Source Address Register */
1252 uint odpr; /* 0xd3018 - Outbound Destination Port Register */
1253 uint odatr; /* 0xd301c - Outbound Destination Attributes Register */
1254 uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */
1255 uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1256 uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
1257 uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */
1258 uint omgr; /* 0xd3030 - Outbound Multicast Group Register */
1259 uint omlr; /* 0xd3034 - Outbound Multicast List Register */
1260 char res52[40];
1261 uint imr; /* 0xd3060 - Outbound Mode Register */
1262 uint isr; /* 0xd3064 - Inbound Status Register */
1263 uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1264 uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
1265 uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
1266 uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
1267 uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
1268 char res53[900];
1269 uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */
1270 uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */
1271 char res54[16];
1272 uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */
1273 uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */
1274 char res55[12];
1275 uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
1276 char res56[48];
1277 uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */
1278 uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */
1279 uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
1280 uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
1281 uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
1282 uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
1283 uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
1284 char res57[100];
1285 uint pwmr; /* 0xd34e0 - Port-Write Mode Register */
1286 uint pwsr; /* 0xd34e4 - Port-Write Status Register */
1287 uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */
1288 uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */
1289 char res58[51984];
1290} ccsr_rio_t;
1291
1292/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
1293typedef struct ccsr_gur {
1294 uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
1295 uint porbmsr; /* 0xe0004 - POR boot mode status register */
1296#define MPC86xx_PORBMSR_HA 0x00060000
1297 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
1298 uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
1299#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
1300 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
1301 char res1[12];
1302 uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
1303 char res2[12];
1304 uint gpiocr; /* 0xe0030 - GPIO control register */
1305 char res3[12];
1306 uint gpoutdr; /* 0xe0040 - General-purpose output data register */
1307 char res4[12];
1308 uint gpindr; /* 0xe0050 - General-purpose input data register */
1309 char res5[12];
1310 uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
1311 char res6[12];
1312 uint devdisr; /* 0xe0070 - Device disable control */
1313#define MPC86xx_DEVDISR_PCIEX1 0x80000000
1314#define MPC86xx_DEVDISR_PCIEX2 0x40000000
1315 char res7[12];
1316 uint powmgtcsr; /* 0xe0080 - Power management status and control register */
1317 char res8[12];
1318 uint mcpsumr; /* 0xe0090 - Machine check summary register */
1319 char res9[12];
1320 uint pvr; /* 0xe00a0 - Processor version register */
1321 uint svr; /* 0xe00a4 - System version register */
1322 char res10[3416];
1323 uint clkocr; /* 0xe0e00 - Clock out select register */
1324 char res11[12];
1325 uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
1326 char res12[12];
1327 uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
1328 int res13[57];
1329 uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/
1330 int res14[6];
1331 uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
1332 char res15[61656];
1333} ccsr_gur_t;
1334
1335typedef struct immap {
1336 ccsr_local_mcm_t im_local_mcm;
1337 ccsr_ddr_t im_ddr1;
1338 ccsr_i2c_t im_i2c;
1339 ccsr_duart_t im_duart;
1340 ccsr_lbc_t im_lbc;
1341 ccsr_ddr_t im_ddr2;
1342 char res1[4096];
1343 ccsr_pex_t im_pex1;
1344 ccsr_pex_t im_pex2;
1345 ccsr_ht_t im_ht;
1346 char res2[90112];
1347 ccsr_dma_t im_dma;
1348 char res3[8192];
1349 ccsr_tsec_t im_tsec1;
1350 ccsr_tsec_t im_tsec2;
1351 ccsr_tsec_t im_tsec3;
1352 ccsr_tsec_t im_tsec4;
1353 char res4[98304];
1354 ccsr_pic_t im_pic;
1355 char res5[389120];
1356 ccsr_rio_t im_rio;
1357 ccsr_gur_t im_gur;
1358} immap_t;
1359
1360extern immap_t *immr;
1361
1362#endif /*__IMMAP_86xx__*/