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git01.mediatek.com / filogic / uboot / 367b510aa080c47c25027982def7f4cf27ab341c / . / board / Arcturus / ucp1020 / tlb.c
blob: 2c07df63e5b5e6463e5a8d639217c76daa6194e7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]2/*
3 * Copyright 2013-2015 Arcturus Networks, Inc
4 * http://www.arcturusnetworks.com/products/ucp1020/
5 * based on board/freescale/p1_p2_rdb_pc/tlb.c
6 * original copyright follows:
7 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]8 */
9
10#include <common.h>
11#include <asm/mmu.h>
12
13struct fsl_e_tlb_entry tlb_table[] = {
14 /* TLB 0 - for temp stack in cache */
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
16 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
17 MAS3_SX | MAS3_SW | MAS3_SR, 0,
18 0, 0, BOOKE_PAGESZ_4K, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
21 MAS3_SX | MAS3_SW | MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
25 MAS3_SX | MAS3_SW | MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0),
27 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
28 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
29 MAS3_SX | MAS3_SW | MAS3_SR, 0,
30 0, 0, BOOKE_PAGESZ_4K, 0),
31
32 /* TLB 1 */
33 /* *I*** - Covers boot page */
34 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
35 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
36 0, 0, BOOKE_PAGESZ_4K, 1),
37
38 /* *I*G* - CCSRBAR */
39 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
40 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
41 0, 1, BOOKE_PAGESZ_1M, 1),
42
43#ifndef CONFIG_SPL_BUILD
44 /* W**G* - Flash/promjet, localbus */
45 /* This will be changed to *I*G* after relocation to RAM. */
46 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
47 MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
48 0, 2, BOOKE_PAGESZ_64M, 1),
49
50#ifdef CONFIG_PCI
51 /* *I*G* - PCI memory 1.5G */
52 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
53 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
54 0, 3, BOOKE_PAGESZ_1G, 1),
55
56 /* *I*G* - PCI I/O effective: 192K */
57 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
58 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
59 0, 4, BOOKE_PAGESZ_256K, 1),
60#endif
61
62#ifdef CONFIG_VSC7385_ENET
63 /* *I*G - VSC7385 Switch */
64 SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
65 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
66 0, 5, BOOKE_PAGESZ_1M, 1),
67#endif
68#endif /* not SPL */
69
70#ifdef CONFIG_SYS_NAND_BASE
71 /* *I*G - NAND */
72 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
73 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
74 0, 7, BOOKE_PAGESZ_1M, 1),
75#endif
76
77#if defined(CONFIG_SYS_RAMBOOT) || \
78 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
79 /* *I*G - eSDHC/eSPI/NAND boot */
80 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
York Sun05204d02017-12-05 10:57:54 -0800[diff] [blame]81 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]82 0, 8, BOOKE_PAGESZ_1G, 1),
83
84#endif /* RAMBOOT/SPL */
85
86#ifdef CONFIG_SYS_INIT_L2_ADDR
87 /* *I*G - L2SRAM */
88 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
89 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
90 0, 11, BOOKE_PAGESZ_256K, 1),
91#if CONFIG_SYS_L2_SIZE >= (256 << 10)
92 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
93 CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
94 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
95 0, 12, BOOKE_PAGESZ_256K, 1)
96#endif
97#endif
98};
99
100int num_tlb_entries = ARRAY_SIZE(tlb_table);