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Lukasz Majewski4de44bb2019-06-24 15:50:45 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 */
6
Patrick Delaunay8767e792021-11-19 15:12:07 +01007#define LOG_CATEGORY UCLASS_CLK
8
Tom Riniabb9a042024-05-18 20:20:43 -06009#include <common.h>
Patrick Delaunay283dadf2021-11-19 15:12:06 +010010#include <clk.h>
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020011#include <clk-uclass.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020013#include <dm/device.h>
14#include <dm/uclass.h>
15#include <dm/lists.h>
16#include <dm/device-internal.h>
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020017
18int clk_register(struct clk *clk, const char *drv_name,
19 const char *name, const char *parent_name)
20{
Yang Xiwen470fba12023-11-11 03:19:52 +080021 struct udevice *parent = NULL;
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020022 struct driver *drv;
23 int ret;
24
Yang Xiwen470fba12023-11-11 03:19:52 +080025 if (parent_name) {
26 ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
27 if (ret) {
28 log_err("%s: failed to get %s device (parent of %s)\n",
29 __func__, parent_name, name);
30 } else {
31 log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name,
32 parent->name, parent);
33 }
Peng Fanc179a172019-10-22 03:31:08 +000034 }
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020035
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020036 drv = lists_driver_lookup_name(drv_name);
37 if (!drv) {
Patrick Delaunay8767e792021-11-19 15:12:07 +010038 log_err("%s: %s is not a valid driver name\n",
39 __func__, drv_name);
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020040 return -ENOENT;
41 }
42
Simon Glass6996c662020-11-28 17:50:03 -070043 ret = device_bind(parent, drv, name, NULL, ofnode_null(), &clk->dev);
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020044 if (ret) {
Patrick Delaunay8767e792021-11-19 15:12:07 +010045 log_err("%s: CLK: %s driver bind error [%d]!\n", __func__, name,
46 ret);
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020047 return ret;
48 }
49
Peng Fan30a6ebc2019-08-21 13:35:03 +000050 clk->enable_count = 0;
Simon Glass95588622020-12-22 19:30:28 -070051
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020052 /* Store back pointer to clk from udevice */
Simon Glass95588622020-12-22 19:30:28 -070053 /* FIXME: This is not allowed...should be allocated by driver model */
54 dev_set_uclass_priv(clk->dev, clk);
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020055
56 return 0;
57}
58
59ulong clk_generic_get_rate(struct clk *clk)
60{
61 return clk_get_parent_rate(clk);
62}
63
64const char *clk_hw_get_name(const struct clk *hw)
65{
Claudiu Beznead3e49d02020-09-07 17:46:32 +030066 assert(hw);
67 assert(hw->dev);
68
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020069 return hw->dev->name;
70}
Peng Fan1d0a50a2019-07-31 07:01:23 +000071
72bool clk_dev_binded(struct clk *clk)
73{
Simon Glass6211d762020-12-19 10:40:10 -070074 if (clk->dev && (dev_get_flags(clk->dev) & DM_FLAG_BOUND))
Peng Fan1d0a50a2019-07-31 07:01:23 +000075 return true;
76
77 return false;
78}
Sean Anderson46596122022-03-20 16:34:45 -040079
80/* Helper functions for clock ops */
81
82ulong ccf_clk_get_rate(struct clk *clk)
83{
84 struct clk *c;
85 int err = clk_get_by_id(clk->id, &c);
86
87 if (err)
88 return err;
89 return clk_get_rate(c);
90}
91
92ulong ccf_clk_set_rate(struct clk *clk, unsigned long rate)
93{
94 struct clk *c;
95 int err = clk_get_by_id(clk->id, &c);
96
97 if (err)
98 return err;
99 return clk_set_rate(c, rate);
100}
101
102int ccf_clk_set_parent(struct clk *clk, struct clk *parent)
103{
104 struct clk *c, *p;
105 int err = clk_get_by_id(clk->id, &c);
106
107 if (err)
108 return err;
109
110 err = clk_get_by_id(parent->id, &p);
111 if (err)
112 return err;
113
114 return clk_set_parent(c, p);
115}
116
117static int ccf_clk_endisable(struct clk *clk, bool enable)
118{
119 struct clk *c;
120 int err = clk_get_by_id(clk->id, &c);
121
122 if (err)
123 return err;
124 return enable ? clk_enable(c) : clk_disable(c);
125}
126
127int ccf_clk_enable(struct clk *clk)
128{
129 return ccf_clk_endisable(clk, true);
130}
131
132int ccf_clk_disable(struct clk *clk)
133{
134 return ccf_clk_endisable(clk, false);
135}
136
137const struct clk_ops ccf_clk_ops = {
138 .set_rate = ccf_clk_set_rate,
139 .get_rate = ccf_clk_get_rate,
140 .set_parent = ccf_clk_set_parent,
141 .enable = ccf_clk_enable,
142 .disable = ccf_clk_disable,
143};