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git01.mediatek.com / filogic / uboot / 34f3e8410ee55a5662078cbbe040e033929a2617 / . / arch / arm / cpu / arm1136 / mx35 / asm-offsets.c
blob: ebd757503941b62392aba098ad7a81bf68351298 [file] [log] [blame]
Stefano Babic1c2b3ac2011-01-20 07:49:52 +0000[diff] [blame]1/*
2 * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3 *
4 * This program is used to generate definitions needed by
5 * assembly language modules.
6 *
7 * We use the technique used in the OSF Mach kernel code:
8 * generate asm statements containing #defines,
9 * compile this file to assembler, and then extract the
10 * #defines from the assembly-language output.
11 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]12 * SPDX-License-Identifier: GPL-2.0+
Stefano Babic1c2b3ac2011-01-20 07:49:52 +0000[diff] [blame]13 */
14
15#include <common.h>
16#include <asm/arch/imx-regs.h>
17
18#include <linux/kbuild.h>
19
20int main(void)
21{
Stefano Babic1c2b3ac2011-01-20 07:49:52 +0000[diff] [blame]22 /* Round up to make sure size gives nice stack alignment */
23 DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
24 DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
25 DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
26 DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
27 DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
28 DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
29 DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
30 DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
31 DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
32 DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
33 DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
34 DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
35 DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
36 DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
Benoît Thébaudeaubc17d2e2012-08-14 11:03:59 +0000[diff] [blame]37 DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
38
39 /* Multi-Layer AHB Crossbar Switch */
40 DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
41 DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
42 DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
43 DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
44 DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
45 DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
46 DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
47 DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
48 DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
49 DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
50 DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
51 DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
52 DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
53 DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
54 DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
55 DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
56
57 /* AHB <-> IP-Bus Interface */
58 DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
59 DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
60 DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
61 DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
62 DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
63 DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
64 DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
65 DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
66 DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
67 DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
68 DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
Stefano Babic1c2b3ac2011-01-20 07:49:52 +0000[diff] [blame]69
70 return 0;
71}