| Nikita Kiryanov | b260492 | 2015-02-03 13:32:20 +0200 | [diff] [blame] | 1 | /* |
| 2 | * exynos_lcd.h - Exynos LCD Controller structures |
| 3 | * |
| 4 | * (C) Copyright 2001 |
| 5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #ifndef _EXYNOS_LCD_H_ |
| 11 | #define _EXYNOS_LCD_H_ |
| 12 | |
| 13 | enum { |
| 14 | FIMD_RGB_INTERFACE = 1, |
| 15 | FIMD_CPU_INTERFACE = 2, |
| 16 | }; |
| 17 | |
| 18 | enum exynos_fb_rgb_mode_t { |
| 19 | MODE_RGB_P = 0, |
| 20 | MODE_BGR_P = 1, |
| 21 | MODE_RGB_S = 2, |
| 22 | MODE_BGR_S = 3, |
| 23 | }; |
| 24 | |
| 25 | typedef struct vidinfo { |
| 26 | ushort vl_col; /* Number of columns (i.e. 640) */ |
| 27 | ushort vl_row; /* Number of rows (i.e. 480) */ |
| 28 | ushort vl_width; /* Width of display area in millimeters */ |
| 29 | ushort vl_height; /* Height of display area in millimeters */ |
| 30 | |
| 31 | /* LCD configuration register */ |
| 32 | u_char vl_freq; /* Frequency */ |
| 33 | u_char vl_clkp; /* Clock polarity */ |
| 34 | u_char vl_oep; /* Output Enable polarity */ |
| 35 | u_char vl_hsp; /* Horizontal Sync polarity */ |
| 36 | u_char vl_vsp; /* Vertical Sync polarity */ |
| 37 | u_char vl_dp; /* Data polarity */ |
| 38 | u_char vl_bpix; /* Bits per pixel */ |
| 39 | |
| 40 | /* Horizontal control register. Timing from data sheet */ |
| 41 | u_char vl_hspw; /* Horz sync pulse width */ |
| 42 | u_char vl_hfpd; /* Wait before of line */ |
| 43 | u_char vl_hbpd; /* Wait end of line */ |
| 44 | |
| 45 | /* Vertical control register. */ |
| 46 | u_char vl_vspw; /* Vertical sync pulse width */ |
| 47 | u_char vl_vfpd; /* Wait before of frame */ |
| 48 | u_char vl_vbpd; /* Wait end of frame */ |
| 49 | u_char vl_cmd_allow_len; /* Wait end of frame */ |
| 50 | |
| 51 | unsigned int win_id; |
| 52 | unsigned int init_delay; |
| 53 | unsigned int power_on_delay; |
| 54 | unsigned int reset_delay; |
| 55 | unsigned int interface_mode; |
| 56 | unsigned int mipi_enabled; |
| 57 | unsigned int dp_enabled; |
| 58 | unsigned int cs_setup; |
| 59 | unsigned int wr_setup; |
| 60 | unsigned int wr_act; |
| 61 | unsigned int wr_hold; |
| 62 | unsigned int logo_on; |
| 63 | unsigned int logo_width; |
| 64 | unsigned int logo_height; |
| 65 | int logo_x_offset; |
| 66 | int logo_y_offset; |
| 67 | unsigned long logo_addr; |
| 68 | unsigned int rgb_mode; |
| 69 | unsigned int resolution; |
| 70 | |
| 71 | /* parent clock name(MPLL, EPLL or VPLL) */ |
| 72 | unsigned int pclk_name; |
| 73 | /* ratio value for source clock from parent clock. */ |
| 74 | unsigned int sclk_div; |
| 75 | |
| 76 | unsigned int dual_lcd_enabled; |
| 77 | } vidinfo_t; |
| 78 | |
| 79 | void init_panel_info(vidinfo_t *vid); |
| 80 | |
| 81 | #endif |